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Fix line endings.
This commit is contained in:
David Brown
parent
c64a75bd78
commit
a9b273e30a
15 changed files with 5328 additions and 5328 deletions
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@ -1,52 +1,52 @@
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MODULE LSB; (*Lola System Compiler Base LSBX, 26.9.2015*)
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IMPORT Texts, Oberon;
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CONST
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bit* = 0; array* = 1; unit* = 2; (*type forms*)
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(*tags in output*) const* = 1; typ* = 2; var* = 3; lit* = 4; sel* = 7; range* = 8; cons* = 9;
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repl* = 10; not* = 11; and* = 12; mul* = 13; div* = 14; or* = 15; xor* = 16; add* = 17; sub* = 18;
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eql* = 20; neq* = 21; lss* = 22; geq* = 23; leq* = 24; gtr* = 25;
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then* = 30; else* = 31; ts* = 32; next* = 33;
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TYPE
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Item* = POINTER TO ItemDesc;
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Object* = POINTER TO ObjDesc;
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Type* = POINTER TO TypeDesc;
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ArrayType* = POINTER TO ArrayTypeDesc;
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UnitType* = POINTER TO UnitTypeDesc;
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ItemDesc* = RECORD
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tag*: INTEGER;
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type*: Type;
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val*, size*: LONGINT;
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a*, b*: Item
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END ;
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ObjDesc* = RECORD (ItemDesc)
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next*: Object;
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name*: ARRAY 32 OF CHAR;
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marked*: BOOLEAN
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END ;
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TypeDesc* = RECORD len*, size*: LONGINT; typobj*: Object END ;
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ArrayTypeDesc* = RECORD (TypeDesc) eltyp*: Type END ;
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UnitTypeDesc* = RECORD (TypeDesc) firstobj*: Object END ;
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VAR root*, top*: Object;
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bitType*, integer*, string*: Type;
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byteType*, wordType*: ArrayType;
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modname*: ARRAY 32 OF CHAR;
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PROCEDURE Register*(name: ARRAY OF CHAR; list: Object);
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BEGIN (*modname := name*) COPY(name, modname); top := list
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END Register;
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BEGIN NEW(bitType); bitType.len := 0; bitType.size := 1; NEW(integer); NEW(string);
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NEW(byteType); byteType.len := 8; byteType.size := 8; byteType.eltyp := bitType;
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NEW(wordType); wordType.len := 32; wordType.size := 32; wordType.eltyp := bitType;
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NEW(root); root.tag := typ; root.name := "WORD"; root.type := wordType; root.next := NIL;
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NEW(top); top.tag := typ; top.name := "BYTE"; top.type := byteType; top.next := root; root := top;
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NEW(top); top.tag := typ; top.name := "BIT"; top.type := bitType; top.next := root; root := top
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END LSB.
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MODULE LSB; (*Lola System Compiler Base LSBX, 26.9.2015*)
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IMPORT Texts, Oberon;
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CONST
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bit* = 0; array* = 1; unit* = 2; (*type forms*)
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(*tags in output*) const* = 1; typ* = 2; var* = 3; lit* = 4; sel* = 7; range* = 8; cons* = 9;
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repl* = 10; not* = 11; and* = 12; mul* = 13; div* = 14; or* = 15; xor* = 16; add* = 17; sub* = 18;
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eql* = 20; neq* = 21; lss* = 22; geq* = 23; leq* = 24; gtr* = 25;
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then* = 30; else* = 31; ts* = 32; next* = 33;
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TYPE
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Item* = POINTER TO ItemDesc;
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Object* = POINTER TO ObjDesc;
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Type* = POINTER TO TypeDesc;
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ArrayType* = POINTER TO ArrayTypeDesc;
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UnitType* = POINTER TO UnitTypeDesc;
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ItemDesc* = RECORD
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tag*: INTEGER;
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type*: Type;
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val*, size*: LONGINT;
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a*, b*: Item
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END ;
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ObjDesc* = RECORD (ItemDesc)
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next*: Object;
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name*: ARRAY 32 OF CHAR;
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marked*: BOOLEAN
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END ;
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TypeDesc* = RECORD len*, size*: LONGINT; typobj*: Object END ;
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ArrayTypeDesc* = RECORD (TypeDesc) eltyp*: Type END ;
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UnitTypeDesc* = RECORD (TypeDesc) firstobj*: Object END ;
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VAR root*, top*: Object;
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bitType*, integer*, string*: Type;
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byteType*, wordType*: ArrayType;
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modname*: ARRAY 32 OF CHAR;
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PROCEDURE Register*(name: ARRAY OF CHAR; list: Object);
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BEGIN (*modname := name*) COPY(name, modname); top := list
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END Register;
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BEGIN NEW(bitType); bitType.len := 0; bitType.size := 1; NEW(integer); NEW(string);
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NEW(byteType); byteType.len := 8; byteType.size := 8; byteType.eltyp := bitType;
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NEW(wordType); wordType.len := 32; wordType.size := 32; wordType.eltyp := bitType;
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NEW(root); root.tag := typ; root.name := "WORD"; root.type := wordType; root.next := NIL;
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NEW(top); top.tag := typ; top.name := "BYTE"; top.type := byteType; top.next := root; root := top;
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NEW(top); top.tag := typ; top.name := "BIT"; top.type := bitType; top.next := root; root := top
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END LSB.
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File diff suppressed because it is too large
Load diff
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@ -1,165 +1,165 @@
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MODULE LSS; (* NW 16.10.93 / 1.9.2015*)
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IMPORT Texts, Oberon;
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CONST IdLen* = 32; NofKeys = 11;
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(*symbols*) null = 0;
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arrow* = 1; times* = 2; div* = 3; and* = 4; plus* = 5; minus* = 6; or* = 7; xor* = 8; not* = 9;
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eql* = 10; neq* = 11; lss* = 12; leq* = 13; gtr* = 14; geq* = 15;
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at* = 16; apo* = 17; period* = 18; comma* = 19; colon* = 20; rparen* = 21; rbrak* = 22; rbrace* = 23;
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then* = 24; lparen* = 26; lbrak* = 27; lbrace* = 28; repl* = 29; becomes* = 30;
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ident* = 31; integer* = 32; ts* = 33; semicolon* = 40; end* = 41;
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const* = 51; type* = 52; reg* = 53; var* = 54; out* = 55; inout* = 56; in* = 57;
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begin* = 58; module* = 59; eof = 60;
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TYPE Ident* = ARRAY IdLen OF CHAR;
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VAR val*: LONGINT;
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id*: Ident;
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error*: BOOLEAN;
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ch: CHAR;
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errpos: LONGINT;
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R: Texts.Reader;
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W: Texts.Writer;
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key: ARRAY NofKeys OF Ident;
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symno: ARRAY NofKeys OF INTEGER;
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PROCEDURE Mark*(msg: ARRAY OF CHAR);
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VAR p: LONGINT;
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BEGIN p := Texts.Pos(R);
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IF p > errpos+2 THEN
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Texts.WriteString(W, " pos "); Texts.WriteInt(W, p, 1);
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Texts.WriteString(W, " err: "); Texts.WriteString(W, msg);
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Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf)
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END ;
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errpos := p; error := TRUE
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END Mark;
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PROCEDURE identifier(VAR sym: INTEGER);
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VAR i: INTEGER;
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BEGIN i := 0;
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REPEAT
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IF i < IdLen THEN id[i] := ch; INC(i) END ;
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Texts.Read(R, ch)
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UNTIL (ch < "0") OR (ch > "9") & (ch < "A") OR (ch > "Z") & (ch < "a") OR (ch > "z");
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IF ch = "'" THEN
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IF i < IdLen THEN id[i] := ch; INC(i) END ;
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Texts.Read(R, ch)
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END ;
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IF i = IdLen THEN Mark("ident too long"); id[IdLen-1] := 0X
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ELSE id[i] := 0X
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END ;
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i := 0;
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WHILE (i < NofKeys) & (id # key[i]) DO INC(i) END ;
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IF i < NofKeys THEN sym := symno[i] ELSE sym := ident END
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END identifier;
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PROCEDURE Number(VAR sym: INTEGER);
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VAR i, k, h, n, d: LONGINT;
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hex: BOOLEAN;
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dig: ARRAY 16 OF LONGINT;
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BEGIN sym := integer; i := 0; k := 0; n := 0; hex := FALSE;
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REPEAT
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IF n < 16 THEN d := ORD(ch)-30H;
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IF d >= 10 THEN hex := TRUE ; d := d - 7 END ;
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dig[n] := d; INC(n)
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ELSE Mark("too many digits"); n := 0
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END ;
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Texts.Read(R, ch)
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UNTIL (ch < "0") OR (ch > "9") & (ch < "A") OR (ch > "F");
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IF ch = "H" THEN (*hex*)
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REPEAT h := dig[i]; k := k*10H + h; INC(i) (*no overflow check*)
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UNTIL i = n;
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Texts.Read(R, ch)
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ELSE
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IF hex THEN Mark("illegal hex digit") END ;
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REPEAT k := k*10 + dig[i]; INC(i) UNTIL i = n
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END ;
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val := k
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END Number;
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PROCEDURE comment;
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BEGIN Texts.Read(R, ch);
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REPEAT
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WHILE ~R.eot & (ch # "*") DO
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IF ch = "(" THEN Texts.Read(R, ch);
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IF ch = "*" THEN comment END
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ELSE Texts.Read(R, ch)
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END
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END ;
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WHILE ch = "*" DO Texts.Read(R, ch) END
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UNTIL (ch = ")") OR R.eot;
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IF ~R.eot THEN Texts.Read(R, ch) ELSE Mark("comment not terminated") END
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END comment;
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PROCEDURE Get*(VAR sym: INTEGER);
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BEGIN
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REPEAT
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WHILE ~R.eot & (ch <= " ") DO Texts.Read(R, ch) END;
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IF R.eot THEN sym := eof
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ELSIF ch < "A" THEN
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IF ch < "0" THEN
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IF ch = "!" THEN Texts.Read(R, ch); sym := repl
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ELSIF ch = "#" THEN Texts.Read(R, ch); sym := neq
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ELSIF ch = "$" THEN Texts.Read(R, ch); sym := null
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ELSIF ch = "&" THEN Texts.Read(R, ch); sym := and
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ELSIF ch = "'" THEN Texts.Read(R, ch); sym := apo
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ELSIF ch = "(" THEN Texts.Read(R, ch);
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IF ch = "*" THEN sym := null; comment ELSE sym := lparen END
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ELSIF ch = ")" THEN Texts.Read(R, ch); sym := rparen
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ELSIF ch = "*" THEN Texts.Read(R, ch); sym := times
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ELSIF ch = "+" THEN Texts.Read(R, ch); sym := plus
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ELSIF ch = "," THEN Texts.Read(R, ch); sym := comma
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ELSIF ch = "-" THEN Texts.Read(R, ch);
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IF ch = ">" THEN Texts.Read(R, ch); sym := then ELSE sym := minus END
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ELSIF ch = "." THEN Texts.Read(R, ch); sym := period
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ELSIF ch = "/" THEN Texts.Read(R, ch); sym := div
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ELSE sym := null
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END
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ELSIF ch <= "9" THEN Number(sym)
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ELSIF ch = ":" THEN Texts.Read(R, ch);
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IF ch = "=" THEN Texts.Read(R, ch); sym := becomes ELSE sym := colon END
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ELSIF ch = ";" THEN Texts.Read(R, ch); sym := semicolon
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ELSIF ch = "<" THEN Texts.Read(R, ch);
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IF ch = "=" THEN Texts.Read(R, ch); sym := leq ELSE sym := lss END
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ELSIF ch = "=" THEN Texts.Read(R, ch); sym := eql
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ELSIF ch = ">" THEN Texts.Read(R, ch);
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IF ch = "=" THEN Texts.Read(R, ch); sym := geq ELSE sym := gtr END
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ELSIF ch = "?" THEN Texts.Read(R, ch); sym := then
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ELSIF ch = "@" THEN Texts.Read(R, ch); sym := at
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ELSE sym := null
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END
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ELSIF ch <= "Z" THEN identifier(sym)
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ELSIF ch < "a" THEN
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IF ch = "[" THEN Texts.Read(R, ch); sym := lbrak
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ELSIF ch = "]" THEN Texts.Read(R, ch); sym := rbrak
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ELSIF ch = "^" THEN Texts.Read(R, ch); sym := xor
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ELSE sym := null
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END
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ELSIF ch <= "z" THEN identifier(sym)
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ELSIF ch <= "{" THEN Texts.Read(R, ch); sym := lbrace
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ELSIF ch <= "|" THEN Texts.Read(R, ch); sym := or
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ELSIF ch <= "}" THEN Texts.Read(R, ch); sym := rbrace
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ELSIF ch <= "~" THEN Texts.Read(R, ch); sym := not
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ELSE sym := null
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END
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UNTIL sym # null
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END Get;
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PROCEDURE Init*(T: Texts.Text; pos: LONGINT);
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BEGIN error := FALSE; errpos := pos; Texts.OpenReader(R, T, pos); Texts.Read(R, ch)
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END Init;
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BEGIN Texts.OpenWriter(W);
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key[ 0] := "BEGIN"; symno[0] := begin;
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key[ 1] := "CONST"; symno[1] := const;
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key[ 2] := "END"; symno[2] := end;
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key[3] := "IN"; symno[3] := in;
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key[4] := "INOUT"; symno[4] := inout;
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key[5] := "MODULE"; symno[5] := module;
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key[6] := "OUT"; symno[6] := out;
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key[7] := "REG"; symno[7] := reg;
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key[8] := "TYPE"; symno[8] := type;
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key[9] := "VAR"; symno[9] := var;
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key[10] := "TS"; symno[10] := ts
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END LSS.
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MODULE LSS; (* NW 16.10.93 / 1.9.2015*)
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IMPORT Texts, Oberon;
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CONST IdLen* = 32; NofKeys = 11;
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(*symbols*) null = 0;
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arrow* = 1; times* = 2; div* = 3; and* = 4; plus* = 5; minus* = 6; or* = 7; xor* = 8; not* = 9;
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eql* = 10; neq* = 11; lss* = 12; leq* = 13; gtr* = 14; geq* = 15;
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at* = 16; apo* = 17; period* = 18; comma* = 19; colon* = 20; rparen* = 21; rbrak* = 22; rbrace* = 23;
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then* = 24; lparen* = 26; lbrak* = 27; lbrace* = 28; repl* = 29; becomes* = 30;
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ident* = 31; integer* = 32; ts* = 33; semicolon* = 40; end* = 41;
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const* = 51; type* = 52; reg* = 53; var* = 54; out* = 55; inout* = 56; in* = 57;
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begin* = 58; module* = 59; eof = 60;
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TYPE Ident* = ARRAY IdLen OF CHAR;
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VAR val*: LONGINT;
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id*: Ident;
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error*: BOOLEAN;
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ch: CHAR;
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errpos: LONGINT;
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R: Texts.Reader;
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W: Texts.Writer;
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key: ARRAY NofKeys OF Ident;
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symno: ARRAY NofKeys OF INTEGER;
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PROCEDURE Mark*(msg: ARRAY OF CHAR);
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VAR p: LONGINT;
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BEGIN p := Texts.Pos(R);
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IF p > errpos+2 THEN
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Texts.WriteString(W, " pos "); Texts.WriteInt(W, p, 1);
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Texts.WriteString(W, " err: "); Texts.WriteString(W, msg);
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Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf)
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END ;
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errpos := p; error := TRUE
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END Mark;
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PROCEDURE identifier(VAR sym: INTEGER);
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VAR i: INTEGER;
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BEGIN i := 0;
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REPEAT
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IF i < IdLen THEN id[i] := ch; INC(i) END ;
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Texts.Read(R, ch)
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UNTIL (ch < "0") OR (ch > "9") & (ch < "A") OR (ch > "Z") & (ch < "a") OR (ch > "z");
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IF ch = "'" THEN
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IF i < IdLen THEN id[i] := ch; INC(i) END ;
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Texts.Read(R, ch)
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END ;
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IF i = IdLen THEN Mark("ident too long"); id[IdLen-1] := 0X
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ELSE id[i] := 0X
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END ;
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i := 0;
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WHILE (i < NofKeys) & (id # key[i]) DO INC(i) END ;
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IF i < NofKeys THEN sym := symno[i] ELSE sym := ident END
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END identifier;
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PROCEDURE Number(VAR sym: INTEGER);
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VAR i, k, h, n, d: LONGINT;
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hex: BOOLEAN;
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dig: ARRAY 16 OF LONGINT;
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BEGIN sym := integer; i := 0; k := 0; n := 0; hex := FALSE;
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REPEAT
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IF n < 16 THEN d := ORD(ch)-30H;
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IF d >= 10 THEN hex := TRUE ; d := d - 7 END ;
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dig[n] := d; INC(n)
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ELSE Mark("too many digits"); n := 0
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END ;
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Texts.Read(R, ch)
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UNTIL (ch < "0") OR (ch > "9") & (ch < "A") OR (ch > "F");
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IF ch = "H" THEN (*hex*)
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REPEAT h := dig[i]; k := k*10H + h; INC(i) (*no overflow check*)
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UNTIL i = n;
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Texts.Read(R, ch)
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ELSE
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IF hex THEN Mark("illegal hex digit") END ;
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REPEAT k := k*10 + dig[i]; INC(i) UNTIL i = n
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END ;
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val := k
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END Number;
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PROCEDURE comment;
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BEGIN Texts.Read(R, ch);
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REPEAT
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WHILE ~R.eot & (ch # "*") DO
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IF ch = "(" THEN Texts.Read(R, ch);
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IF ch = "*" THEN comment END
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ELSE Texts.Read(R, ch)
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END
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END ;
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WHILE ch = "*" DO Texts.Read(R, ch) END
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UNTIL (ch = ")") OR R.eot;
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IF ~R.eot THEN Texts.Read(R, ch) ELSE Mark("comment not terminated") END
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END comment;
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PROCEDURE Get*(VAR sym: INTEGER);
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BEGIN
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REPEAT
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WHILE ~R.eot & (ch <= " ") DO Texts.Read(R, ch) END;
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IF R.eot THEN sym := eof
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ELSIF ch < "A" THEN
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IF ch < "0" THEN
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IF ch = "!" THEN Texts.Read(R, ch); sym := repl
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ELSIF ch = "#" THEN Texts.Read(R, ch); sym := neq
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ELSIF ch = "$" THEN Texts.Read(R, ch); sym := null
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ELSIF ch = "&" THEN Texts.Read(R, ch); sym := and
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ELSIF ch = "'" THEN Texts.Read(R, ch); sym := apo
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ELSIF ch = "(" THEN Texts.Read(R, ch);
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IF ch = "*" THEN sym := null; comment ELSE sym := lparen END
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ELSIF ch = ")" THEN Texts.Read(R, ch); sym := rparen
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ELSIF ch = "*" THEN Texts.Read(R, ch); sym := times
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ELSIF ch = "+" THEN Texts.Read(R, ch); sym := plus
|
||||
ELSIF ch = "," THEN Texts.Read(R, ch); sym := comma
|
||||
ELSIF ch = "-" THEN Texts.Read(R, ch);
|
||||
IF ch = ">" THEN Texts.Read(R, ch); sym := then ELSE sym := minus END
|
||||
ELSIF ch = "." THEN Texts.Read(R, ch); sym := period
|
||||
ELSIF ch = "/" THEN Texts.Read(R, ch); sym := div
|
||||
ELSE sym := null
|
||||
END
|
||||
ELSIF ch <= "9" THEN Number(sym)
|
||||
ELSIF ch = ":" THEN Texts.Read(R, ch);
|
||||
IF ch = "=" THEN Texts.Read(R, ch); sym := becomes ELSE sym := colon END
|
||||
ELSIF ch = ";" THEN Texts.Read(R, ch); sym := semicolon
|
||||
ELSIF ch = "<" THEN Texts.Read(R, ch);
|
||||
IF ch = "=" THEN Texts.Read(R, ch); sym := leq ELSE sym := lss END
|
||||
ELSIF ch = "=" THEN Texts.Read(R, ch); sym := eql
|
||||
ELSIF ch = ">" THEN Texts.Read(R, ch);
|
||||
IF ch = "=" THEN Texts.Read(R, ch); sym := geq ELSE sym := gtr END
|
||||
ELSIF ch = "?" THEN Texts.Read(R, ch); sym := then
|
||||
ELSIF ch = "@" THEN Texts.Read(R, ch); sym := at
|
||||
ELSE sym := null
|
||||
END
|
||||
ELSIF ch <= "Z" THEN identifier(sym)
|
||||
ELSIF ch < "a" THEN
|
||||
IF ch = "[" THEN Texts.Read(R, ch); sym := lbrak
|
||||
ELSIF ch = "]" THEN Texts.Read(R, ch); sym := rbrak
|
||||
ELSIF ch = "^" THEN Texts.Read(R, ch); sym := xor
|
||||
ELSE sym := null
|
||||
END
|
||||
ELSIF ch <= "z" THEN identifier(sym)
|
||||
ELSIF ch <= "{" THEN Texts.Read(R, ch); sym := lbrace
|
||||
ELSIF ch <= "|" THEN Texts.Read(R, ch); sym := or
|
||||
ELSIF ch <= "}" THEN Texts.Read(R, ch); sym := rbrace
|
||||
ELSIF ch <= "~" THEN Texts.Read(R, ch); sym := not
|
||||
ELSE sym := null
|
||||
END
|
||||
UNTIL sym # null
|
||||
END Get;
|
||||
|
||||
PROCEDURE Init*(T: Texts.Text; pos: LONGINT);
|
||||
BEGIN error := FALSE; errpos := pos; Texts.OpenReader(R, T, pos); Texts.Read(R, ch)
|
||||
END Init;
|
||||
|
||||
BEGIN Texts.OpenWriter(W);
|
||||
key[ 0] := "BEGIN"; symno[0] := begin;
|
||||
key[ 1] := "CONST"; symno[1] := const;
|
||||
key[ 2] := "END"; symno[2] := end;
|
||||
key[3] := "IN"; symno[3] := in;
|
||||
key[4] := "INOUT"; symno[4] := inout;
|
||||
key[5] := "MODULE"; symno[5] := module;
|
||||
key[6] := "OUT"; symno[6] := out;
|
||||
key[7] := "REG"; symno[7] := reg;
|
||||
key[8] := "TYPE"; symno[8] := type;
|
||||
key[9] := "VAR"; symno[9] := var;
|
||||
key[10] := "TS"; symno[10] := ts
|
||||
END LSS.
|
||||
|
|
|
|||
|
|
@ -1,238 +1,238 @@
|
|||
MODULE LSV; (*Lola System: display Verilog; generate txt-File; NW 31.8.2015*)
|
||||
IMPORT Files, Texts, Oberon, LSB;
|
||||
|
||||
VAR W: Texts.Writer;
|
||||
nofgen: INTEGER;
|
||||
Constructor: PROCEDURE (VAR x: LSB.Item); (*to avoid forward reference*)
|
||||
F: Files.File; R: Files.Rider;
|
||||
C: ARRAY 64, 6 OF CHAR;
|
||||
|
||||
PROCEDURE Write(ch: CHAR);
|
||||
BEGIN Files.Write(R, ch)
|
||||
END Write;
|
||||
|
||||
PROCEDURE WriteLn;
|
||||
BEGIN Files.Write(R, 0DX); Files.Write(R, 0AX)
|
||||
END WriteLn;
|
||||
|
||||
PROCEDURE WriteInt(x: LONGINT); (* x >= 0 *)
|
||||
VAR i: INTEGER; d: ARRAY 14 OF LONGINT;
|
||||
BEGIN i := 0;
|
||||
IF x < 0 THEN Files.Write(R, "-"); x := -x END ;
|
||||
REPEAT d[i] := x MOD 10; x := x DIV 10; INC(i) UNTIL x = 0;
|
||||
REPEAT DEC(i); Files.Write(R, CHR(d[i] + 30H)) UNTIL i = 0
|
||||
END WriteInt;
|
||||
|
||||
PROCEDURE WriteHex(x: LONGINT); (*x >= 0*)
|
||||
VAR i: INTEGER; d: ARRAY 8 OF LONGINT;
|
||||
BEGIN i := 0;
|
||||
REPEAT d[i] := x MOD 10H; x := x DIV 10H; INC(i) UNTIL (x = 0) OR (i = 8);
|
||||
REPEAT DEC(i);
|
||||
IF d[i] >= 10 THEN Files.Write(R, CHR(d[i] + 37H)) ELSE Files.Write(R, CHR(d[i] + 30H)) END
|
||||
UNTIL i = 0
|
||||
END WriteHex;
|
||||
|
||||
PROCEDURE WriteString(s: ARRAY OF CHAR);
|
||||
VAR i: INTEGER;
|
||||
BEGIN i := 0;
|
||||
WHILE s[i] # 0X DO Files.Write(R, s[i]); INC(i) END
|
||||
END WriteString;
|
||||
|
||||
(* ------------------------------- *)
|
||||
|
||||
PROCEDURE Type(typ: LSB.Type);
|
||||
VAR obj: LSB.Object;
|
||||
BEGIN
|
||||
IF typ IS LSB.ArrayType THEN
|
||||
IF typ(LSB.ArrayType).eltyp # LSB.bitType THEN
|
||||
Write("["); WriteInt(typ.len - 1); WriteString(":0]"); Type(typ(LSB.ArrayType).eltyp)
|
||||
END
|
||||
ELSIF typ IS LSB.UnitType THEN (* obj := typ(LSB.UnitType).firstobj; *)
|
||||
END
|
||||
END Type;
|
||||
|
||||
PROCEDURE BitArrLen(typ: LSB.Type);
|
||||
VAR eltyp: LSB.Type;
|
||||
BEGIN
|
||||
IF typ IS LSB.ArrayType THEN
|
||||
eltyp := typ(LSB.ArrayType).eltyp;
|
||||
WHILE eltyp IS LSB.ArrayType DO typ := eltyp; eltyp := typ(LSB.ArrayType).eltyp END ;
|
||||
IF eltyp = LSB.bitType THEN
|
||||
Write("["); WriteInt(typ.len - 1);WriteString(":0] ")
|
||||
END
|
||||
END
|
||||
END BitArrLen;
|
||||
|
||||
PROCEDURE Expression(x: LSB.Item);
|
||||
VAR z: LSB.Item;
|
||||
BEGIN
|
||||
IF x # NIL THEN
|
||||
IF x IS LSB.Object THEN WriteString(x(LSB.Object).name)
|
||||
ELSIF x.tag = LSB.cons THEN
|
||||
Write("{"); Constructor(x); Write("}")
|
||||
ELSE
|
||||
IF x.tag = LSB.repl THEN
|
||||
Write("{"); WriteInt(x.b.val); Write("{"); Expression(x.a);
|
||||
Write("}"); Write("}")
|
||||
ELSE
|
||||
IF (x.tag >= LSB.and) & (x.tag <= LSB.gtr) THEN Write("(") END ;
|
||||
Expression(x.a);
|
||||
IF x.tag = LSB.sel THEN Write("["); Expression(x.b); Write("]")
|
||||
ELSIF x.tag = LSB.lit THEN
|
||||
IF x.size # 0 THEN WriteInt(x.size); Write("'"); Write("h"); WriteHex(x.val)
|
||||
ELSE WriteInt(x.val)
|
||||
END
|
||||
ELSE WriteString(C[x.tag]); Expression(x.b)
|
||||
END ;
|
||||
IF (x.tag >= LSB.and) & (x.tag <= LSB.gtr) THEN Write(")") END
|
||||
END
|
||||
END
|
||||
END
|
||||
END Expression;
|
||||
|
||||
PROCEDURE Elem(VAR x: LSB.Item);
|
||||
BEGIN
|
||||
IF x.tag = LSB.repl THEN
|
||||
Write("{"); WriteInt(x.b.val); Write("{"); Expression(x.a); WriteString("}}")
|
||||
ELSE Expression(x)
|
||||
END
|
||||
END Elem;
|
||||
|
||||
PROCEDURE Constructor0(VAR x: LSB.Item);
|
||||
BEGIN
|
||||
IF x.tag = LSB.cons THEN Constructor(x.a); WriteString(", "); Elem(x.b) ELSE Elem(x) END
|
||||
END Constructor0;
|
||||
|
||||
PROCEDURE Declaration(obj: LSB.Object);
|
||||
VAR apar: LSB.Item; typ: LSB.Type;
|
||||
BEGIN typ := obj.type;
|
||||
IF obj.type IS LSB.UnitType THEN WriteString("unit ") ELSE Type(obj.type) END ;
|
||||
IF obj.tag = LSB.var THEN
|
||||
IF obj.type IS LSB.UnitType THEN
|
||||
apar := obj.a; WriteLn; Write("[");
|
||||
WHILE apar # NIL DO Expression(apar.b); apar := apar.a END ;
|
||||
Write("]")
|
||||
END
|
||||
ELSIF obj.tag = LSB.const THEN WriteString(" = "); WriteInt(obj.val)
|
||||
END
|
||||
END Declaration;
|
||||
|
||||
PROCEDURE ObjList0(obj: LSB.Object); (*declarations*)
|
||||
VAR obj1: LSB.Object; param: BOOLEAN;
|
||||
BEGIN param := TRUE;
|
||||
WHILE obj # LSB.root DO
|
||||
IF (obj.tag = LSB.var) & ~(obj.type IS LSB.UnitType) THEN
|
||||
IF obj.val <= 1 THEN WriteString("reg ")
|
||||
ELSIF obj.val = 2 THEN WriteString("wire ")
|
||||
ELSIF obj.val = 3 THEN WriteString("output ")
|
||||
ELSIF obj.val = 4 THEN WriteString("output reg ")
|
||||
ELSIF obj.val = 5 THEN WriteString("inout ")
|
||||
ELSIF obj.val = 6 THEN WriteString("input ")
|
||||
ELSE WriteString("??? ")
|
||||
END ;
|
||||
BitArrLen(obj.type); WriteString(obj.name);
|
||||
obj1 := obj.next;
|
||||
WHILE (obj1 # LSB.top) & (obj1.type = obj.type) & (obj1.val = obj.val) DO
|
||||
WriteString(", "); obj := obj1; WriteString(obj.name); obj1 := obj.next
|
||||
END ;
|
||||
IF param & (obj.val >= 3) & (obj1.val < 3) THEN (*end param list*) param := FALSE; Write(")")
|
||||
END ;
|
||||
IF (obj.type # LSB.bitType) & (obj.type(LSB.ArrayType).eltyp # LSB.bitType) THEN Type(obj.type) END ;
|
||||
IF param THEN Write(",") ELSE Write(";") END ;
|
||||
WriteLn
|
||||
ELSIF obj.tag = LSB.const THEN
|
||||
END ;
|
||||
obj := obj.next
|
||||
END
|
||||
END ObjList0;
|
||||
|
||||
PROCEDURE ActParam(VAR x: LSB.Item; fpar: LSB.Object);
|
||||
BEGIN Write("."); WriteString(fpar.name); Write("("); Expression(x); Write(")")
|
||||
END ActParam;
|
||||
|
||||
PROCEDURE ObjList1(obj: LSB.Object); (*assignments to variables*)
|
||||
VAR apar, x: LSB.Item; fpar: LSB.Object; size: LONGINT;
|
||||
BEGIN
|
||||
WHILE obj # LSB.root DO
|
||||
IF (obj.tag = LSB.var) OR (obj.tag = LSB.const) THEN
|
||||
IF obj.type IS LSB.UnitType THEN
|
||||
WriteString(obj.type.typobj.name); Write(" "); WriteString(obj.name);
|
||||
apar := obj.b; fpar := obj.type(LSB.UnitType).firstobj;
|
||||
Write("("); ActParam(apar.b, fpar); apar := apar.a; fpar := fpar.next; (*actual param list*)
|
||||
WHILE apar # NIL DO WriteString(", "); ActParam(apar.b, fpar); apar := apar.a; fpar := fpar.next END ;
|
||||
Write(")"); Write(";"); WriteLn
|
||||
ELSIF (obj.b # NIL) & (obj.val = 5) THEN (*tri-state*)
|
||||
size := obj.type.size; x := obj.b;
|
||||
IF x.tag = LSB.ts THEN
|
||||
IF obj.type = LSB.bitType THEN
|
||||
WriteString("IOBUF block"); INC(nofgen); WriteInt(nofgen); WriteString(" (.IO("); WriteString(obj.name);
|
||||
WriteString("), .O("); WriteString(x.a(LSB.Object).name); WriteString("), .I("); x := x.b;
|
||||
IF x.a.type = LSB.bitType THEN Expression(x.a) ELSE WriteString(x.a(LSB.Object).name) END ;
|
||||
WriteString("), .T(");
|
||||
IF x.b.type = LSB.bitType THEN Expression(x.b) ELSE WriteString(x.b(LSB.Object).name) END ;
|
||||
WriteString("));")
|
||||
ELSE (*array type*)
|
||||
IF nofgen = 0 THEN WriteString("genvar i;"); WriteLn END ;
|
||||
INC(nofgen); WriteString("generate"); WriteLn;
|
||||
WriteString("for (i = 0; i < "); WriteInt(size); WriteString("; i = i+1) begin : bufblock"); WriteInt(nofgen); WriteLn;
|
||||
WriteString("IOBUF block (.IO("); WriteString(obj.name);
|
||||
WriteString("[i]), .O("); WriteString(x.a(LSB.Object).name); WriteString("[i]), .I("); x := x.b;
|
||||
WriteString(x.a(LSB.Object).name); WriteString("[i]), .T(");
|
||||
IF x.b.type = LSB.bitType THEN Expression(x.b) ELSE WriteString(x.b(LSB.Object).name); WriteString("[i]") END ;
|
||||
WriteString("));"); WriteLn; WriteString("end"); WriteLn; WriteString("endgenerate")
|
||||
END ;
|
||||
WriteLn
|
||||
END
|
||||
ELSIF (obj.b # NIL) & (obj.val >= 2) THEN
|
||||
WriteString("assign "); WriteString(obj.name);
|
||||
IF (obj.a # NIL) THEN Write("["); Expression(obj.a); Write("]") END ;
|
||||
WriteString(" = "); Expression(obj.b); Write(";"); WriteLn
|
||||
END
|
||||
ELSIF obj.tag = LSB.typ THEN (*instantiation; actual parameters*)
|
||||
END ;
|
||||
obj := obj.next
|
||||
END
|
||||
END ObjList1;
|
||||
|
||||
PROCEDURE ObjList2(obj: LSB.Object); (*assignments to registers*)
|
||||
VAR apar: LSB.Item; kind: LONGINT; clk: LSB.Item;
|
||||
BEGIN
|
||||
WHILE obj # LSB.root DO
|
||||
IF (obj.tag = LSB.var) & ~(obj.type IS LSB.UnitType) & (obj.val < 2) THEN
|
||||
WriteString("always @ (posedge "); kind := obj.val;
|
||||
IF kind = 0 THEN Expression(obj.a)
|
||||
ELSE (*kind = 1*) WriteString("clk")
|
||||
END ;
|
||||
WriteString(") begin ");
|
||||
REPEAT WriteString(obj.name);
|
||||
IF (kind = 1) & (obj.a # NIL) THEN Write("["); Expression(obj.a); Write("]") END ;
|
||||
WriteString(" <= "); Expression(obj.b); Write(";"); WriteLn; obj := obj.next
|
||||
UNTIL (obj = LSB.top) OR (obj.val # kind);
|
||||
WriteString("end"); WriteLn
|
||||
ELSE obj := obj.next
|
||||
END
|
||||
END
|
||||
END ObjList2;
|
||||
|
||||
PROCEDURE List*;
|
||||
VAR S: Texts.Scanner;
|
||||
BEGIN Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S);
|
||||
IF (S.class = Texts.Name) OR (S.class = Texts.String) THEN
|
||||
Texts.WriteString(W, LSB.modname); Texts.WriteString(W, " translating to "); Texts.WriteString(W, S.s);
|
||||
F := Files.New(S.s); Files.Set(R, F, 0);
|
||||
WriteString("`timescale 1ns / 1 ps"); WriteLn; nofgen := 0;
|
||||
WriteString("module "); WriteString(LSB.modname); WriteString("( // translated from Lola"); WriteLn;
|
||||
ObjList0(LSB.top); ObjList1(LSB.top); ObjList2(LSB.top);
|
||||
WriteString("endmodule"); WriteLn;
|
||||
Files.Register(F); Texts.WriteString(W, " done"); Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf)
|
||||
END
|
||||
END List;
|
||||
|
||||
BEGIN Texts.OpenWriter(W); Constructor := Constructor0;
|
||||
C[LSB.const] := "CONST"; C[LSB.typ] := "TYPE"; C[LSB.var] := "VAR";
|
||||
C[LSB.lit] := "LIT"; C[LSB.sel] := "SEL"; C[LSB.range] := ":"; C[LSB.cons] := ",";
|
||||
C[LSB.or] := " | "; C[LSB.xor] := " ^ "; C[LSB.and] := " & "; C[LSB.not] := "~";
|
||||
C[LSB.add] := " + "; C[LSB.sub] := " - "; C[LSB.mul] := " * "; C[LSB.div] := " / ";
|
||||
C[LSB.eql] := " == "; C[LSB.neq] := " != "; C[LSB.lss] := " < "; C[LSB.geq] := " >= "; C[LSB.leq] := " <= "; C[LSB.gtr] := " > ";
|
||||
C[LSB.then] := " ? "; C[LSB.else] := " : "; C[LSB.ts] := "TS"; C[LSB.next] := "--"
|
||||
END LSV.
|
||||
MODULE LSV; (*Lola System: display Verilog; generate txt-File; NW 31.8.2015*)
|
||||
IMPORT Files, Texts, Oberon, LSB;
|
||||
|
||||
VAR W: Texts.Writer;
|
||||
nofgen: INTEGER;
|
||||
Constructor: PROCEDURE (VAR x: LSB.Item); (*to avoid forward reference*)
|
||||
F: Files.File; R: Files.Rider;
|
||||
C: ARRAY 64, 6 OF CHAR;
|
||||
|
||||
PROCEDURE Write(ch: CHAR);
|
||||
BEGIN Files.Write(R, ch)
|
||||
END Write;
|
||||
|
||||
PROCEDURE WriteLn;
|
||||
BEGIN Files.Write(R, 0DX); Files.Write(R, 0AX)
|
||||
END WriteLn;
|
||||
|
||||
PROCEDURE WriteInt(x: LONGINT); (* x >= 0 *)
|
||||
VAR i: INTEGER; d: ARRAY 14 OF LONGINT;
|
||||
BEGIN i := 0;
|
||||
IF x < 0 THEN Files.Write(R, "-"); x := -x END ;
|
||||
REPEAT d[i] := x MOD 10; x := x DIV 10; INC(i) UNTIL x = 0;
|
||||
REPEAT DEC(i); Files.Write(R, CHR(d[i] + 30H)) UNTIL i = 0
|
||||
END WriteInt;
|
||||
|
||||
PROCEDURE WriteHex(x: LONGINT); (*x >= 0*)
|
||||
VAR i: INTEGER; d: ARRAY 8 OF LONGINT;
|
||||
BEGIN i := 0;
|
||||
REPEAT d[i] := x MOD 10H; x := x DIV 10H; INC(i) UNTIL (x = 0) OR (i = 8);
|
||||
REPEAT DEC(i);
|
||||
IF d[i] >= 10 THEN Files.Write(R, CHR(d[i] + 37H)) ELSE Files.Write(R, CHR(d[i] + 30H)) END
|
||||
UNTIL i = 0
|
||||
END WriteHex;
|
||||
|
||||
PROCEDURE WriteString(s: ARRAY OF CHAR);
|
||||
VAR i: INTEGER;
|
||||
BEGIN i := 0;
|
||||
WHILE s[i] # 0X DO Files.Write(R, s[i]); INC(i) END
|
||||
END WriteString;
|
||||
|
||||
(* ------------------------------- *)
|
||||
|
||||
PROCEDURE Type(typ: LSB.Type);
|
||||
VAR obj: LSB.Object;
|
||||
BEGIN
|
||||
IF typ IS LSB.ArrayType THEN
|
||||
IF typ(LSB.ArrayType).eltyp # LSB.bitType THEN
|
||||
Write("["); WriteInt(typ.len - 1); WriteString(":0]"); Type(typ(LSB.ArrayType).eltyp)
|
||||
END
|
||||
ELSIF typ IS LSB.UnitType THEN (* obj := typ(LSB.UnitType).firstobj; *)
|
||||
END
|
||||
END Type;
|
||||
|
||||
PROCEDURE BitArrLen(typ: LSB.Type);
|
||||
VAR eltyp: LSB.Type;
|
||||
BEGIN
|
||||
IF typ IS LSB.ArrayType THEN
|
||||
eltyp := typ(LSB.ArrayType).eltyp;
|
||||
WHILE eltyp IS LSB.ArrayType DO typ := eltyp; eltyp := typ(LSB.ArrayType).eltyp END ;
|
||||
IF eltyp = LSB.bitType THEN
|
||||
Write("["); WriteInt(typ.len - 1);WriteString(":0] ")
|
||||
END
|
||||
END
|
||||
END BitArrLen;
|
||||
|
||||
PROCEDURE Expression(x: LSB.Item);
|
||||
VAR z: LSB.Item;
|
||||
BEGIN
|
||||
IF x # NIL THEN
|
||||
IF x IS LSB.Object THEN WriteString(x(LSB.Object).name)
|
||||
ELSIF x.tag = LSB.cons THEN
|
||||
Write("{"); Constructor(x); Write("}")
|
||||
ELSE
|
||||
IF x.tag = LSB.repl THEN
|
||||
Write("{"); WriteInt(x.b.val); Write("{"); Expression(x.a);
|
||||
Write("}"); Write("}")
|
||||
ELSE
|
||||
IF (x.tag >= LSB.and) & (x.tag <= LSB.gtr) THEN Write("(") END ;
|
||||
Expression(x.a);
|
||||
IF x.tag = LSB.sel THEN Write("["); Expression(x.b); Write("]")
|
||||
ELSIF x.tag = LSB.lit THEN
|
||||
IF x.size # 0 THEN WriteInt(x.size); Write("'"); Write("h"); WriteHex(x.val)
|
||||
ELSE WriteInt(x.val)
|
||||
END
|
||||
ELSE WriteString(C[x.tag]); Expression(x.b)
|
||||
END ;
|
||||
IF (x.tag >= LSB.and) & (x.tag <= LSB.gtr) THEN Write(")") END
|
||||
END
|
||||
END
|
||||
END
|
||||
END Expression;
|
||||
|
||||
PROCEDURE Elem(VAR x: LSB.Item);
|
||||
BEGIN
|
||||
IF x.tag = LSB.repl THEN
|
||||
Write("{"); WriteInt(x.b.val); Write("{"); Expression(x.a); WriteString("}}")
|
||||
ELSE Expression(x)
|
||||
END
|
||||
END Elem;
|
||||
|
||||
PROCEDURE Constructor0(VAR x: LSB.Item);
|
||||
BEGIN
|
||||
IF x.tag = LSB.cons THEN Constructor(x.a); WriteString(", "); Elem(x.b) ELSE Elem(x) END
|
||||
END Constructor0;
|
||||
|
||||
PROCEDURE Declaration(obj: LSB.Object);
|
||||
VAR apar: LSB.Item; typ: LSB.Type;
|
||||
BEGIN typ := obj.type;
|
||||
IF obj.type IS LSB.UnitType THEN WriteString("unit ") ELSE Type(obj.type) END ;
|
||||
IF obj.tag = LSB.var THEN
|
||||
IF obj.type IS LSB.UnitType THEN
|
||||
apar := obj.a; WriteLn; Write("[");
|
||||
WHILE apar # NIL DO Expression(apar.b); apar := apar.a END ;
|
||||
Write("]")
|
||||
END
|
||||
ELSIF obj.tag = LSB.const THEN WriteString(" = "); WriteInt(obj.val)
|
||||
END
|
||||
END Declaration;
|
||||
|
||||
PROCEDURE ObjList0(obj: LSB.Object); (*declarations*)
|
||||
VAR obj1: LSB.Object; param: BOOLEAN;
|
||||
BEGIN param := TRUE;
|
||||
WHILE obj # LSB.root DO
|
||||
IF (obj.tag = LSB.var) & ~(obj.type IS LSB.UnitType) THEN
|
||||
IF obj.val <= 1 THEN WriteString("reg ")
|
||||
ELSIF obj.val = 2 THEN WriteString("wire ")
|
||||
ELSIF obj.val = 3 THEN WriteString("output ")
|
||||
ELSIF obj.val = 4 THEN WriteString("output reg ")
|
||||
ELSIF obj.val = 5 THEN WriteString("inout ")
|
||||
ELSIF obj.val = 6 THEN WriteString("input ")
|
||||
ELSE WriteString("??? ")
|
||||
END ;
|
||||
BitArrLen(obj.type); WriteString(obj.name);
|
||||
obj1 := obj.next;
|
||||
WHILE (obj1 # LSB.top) & (obj1.type = obj.type) & (obj1.val = obj.val) DO
|
||||
WriteString(", "); obj := obj1; WriteString(obj.name); obj1 := obj.next
|
||||
END ;
|
||||
IF param & (obj.val >= 3) & (obj1.val < 3) THEN (*end param list*) param := FALSE; Write(")")
|
||||
END ;
|
||||
IF (obj.type # LSB.bitType) & (obj.type(LSB.ArrayType).eltyp # LSB.bitType) THEN Type(obj.type) END ;
|
||||
IF param THEN Write(",") ELSE Write(";") END ;
|
||||
WriteLn
|
||||
ELSIF obj.tag = LSB.const THEN
|
||||
END ;
|
||||
obj := obj.next
|
||||
END
|
||||
END ObjList0;
|
||||
|
||||
PROCEDURE ActParam(VAR x: LSB.Item; fpar: LSB.Object);
|
||||
BEGIN Write("."); WriteString(fpar.name); Write("("); Expression(x); Write(")")
|
||||
END ActParam;
|
||||
|
||||
PROCEDURE ObjList1(obj: LSB.Object); (*assignments to variables*)
|
||||
VAR apar, x: LSB.Item; fpar: LSB.Object; size: LONGINT;
|
||||
BEGIN
|
||||
WHILE obj # LSB.root DO
|
||||
IF (obj.tag = LSB.var) OR (obj.tag = LSB.const) THEN
|
||||
IF obj.type IS LSB.UnitType THEN
|
||||
WriteString(obj.type.typobj.name); Write(" "); WriteString(obj.name);
|
||||
apar := obj.b; fpar := obj.type(LSB.UnitType).firstobj;
|
||||
Write("("); ActParam(apar.b, fpar); apar := apar.a; fpar := fpar.next; (*actual param list*)
|
||||
WHILE apar # NIL DO WriteString(", "); ActParam(apar.b, fpar); apar := apar.a; fpar := fpar.next END ;
|
||||
Write(")"); Write(";"); WriteLn
|
||||
ELSIF (obj.b # NIL) & (obj.val = 5) THEN (*tri-state*)
|
||||
size := obj.type.size; x := obj.b;
|
||||
IF x.tag = LSB.ts THEN
|
||||
IF obj.type = LSB.bitType THEN
|
||||
WriteString("IOBUF block"); INC(nofgen); WriteInt(nofgen); WriteString(" (.IO("); WriteString(obj.name);
|
||||
WriteString("), .O("); WriteString(x.a(LSB.Object).name); WriteString("), .I("); x := x.b;
|
||||
IF x.a.type = LSB.bitType THEN Expression(x.a) ELSE WriteString(x.a(LSB.Object).name) END ;
|
||||
WriteString("), .T(");
|
||||
IF x.b.type = LSB.bitType THEN Expression(x.b) ELSE WriteString(x.b(LSB.Object).name) END ;
|
||||
WriteString("));")
|
||||
ELSE (*array type*)
|
||||
IF nofgen = 0 THEN WriteString("genvar i;"); WriteLn END ;
|
||||
INC(nofgen); WriteString("generate"); WriteLn;
|
||||
WriteString("for (i = 0; i < "); WriteInt(size); WriteString("; i = i+1) begin : bufblock"); WriteInt(nofgen); WriteLn;
|
||||
WriteString("IOBUF block (.IO("); WriteString(obj.name);
|
||||
WriteString("[i]), .O("); WriteString(x.a(LSB.Object).name); WriteString("[i]), .I("); x := x.b;
|
||||
WriteString(x.a(LSB.Object).name); WriteString("[i]), .T(");
|
||||
IF x.b.type = LSB.bitType THEN Expression(x.b) ELSE WriteString(x.b(LSB.Object).name); WriteString("[i]") END ;
|
||||
WriteString("));"); WriteLn; WriteString("end"); WriteLn; WriteString("endgenerate")
|
||||
END ;
|
||||
WriteLn
|
||||
END
|
||||
ELSIF (obj.b # NIL) & (obj.val >= 2) THEN
|
||||
WriteString("assign "); WriteString(obj.name);
|
||||
IF (obj.a # NIL) THEN Write("["); Expression(obj.a); Write("]") END ;
|
||||
WriteString(" = "); Expression(obj.b); Write(";"); WriteLn
|
||||
END
|
||||
ELSIF obj.tag = LSB.typ THEN (*instantiation; actual parameters*)
|
||||
END ;
|
||||
obj := obj.next
|
||||
END
|
||||
END ObjList1;
|
||||
|
||||
PROCEDURE ObjList2(obj: LSB.Object); (*assignments to registers*)
|
||||
VAR apar: LSB.Item; kind: LONGINT; clk: LSB.Item;
|
||||
BEGIN
|
||||
WHILE obj # LSB.root DO
|
||||
IF (obj.tag = LSB.var) & ~(obj.type IS LSB.UnitType) & (obj.val < 2) THEN
|
||||
WriteString("always @ (posedge "); kind := obj.val;
|
||||
IF kind = 0 THEN Expression(obj.a)
|
||||
ELSE (*kind = 1*) WriteString("clk")
|
||||
END ;
|
||||
WriteString(") begin ");
|
||||
REPEAT WriteString(obj.name);
|
||||
IF (kind = 1) & (obj.a # NIL) THEN Write("["); Expression(obj.a); Write("]") END ;
|
||||
WriteString(" <= "); Expression(obj.b); Write(";"); WriteLn; obj := obj.next
|
||||
UNTIL (obj = LSB.top) OR (obj.val # kind);
|
||||
WriteString("end"); WriteLn
|
||||
ELSE obj := obj.next
|
||||
END
|
||||
END
|
||||
END ObjList2;
|
||||
|
||||
PROCEDURE List*;
|
||||
VAR S: Texts.Scanner;
|
||||
BEGIN Texts.OpenScanner(S, Oberon.Par.text, Oberon.Par.pos); Texts.Scan(S);
|
||||
IF (S.class = Texts.Name) OR (S.class = Texts.String) THEN
|
||||
Texts.WriteString(W, LSB.modname); Texts.WriteString(W, " translating to "); Texts.WriteString(W, S.s);
|
||||
F := Files.New(S.s); Files.Set(R, F, 0);
|
||||
WriteString("`timescale 1ns / 1 ps"); WriteLn; nofgen := 0;
|
||||
WriteString("module "); WriteString(LSB.modname); WriteString("( // translated from Lola"); WriteLn;
|
||||
ObjList0(LSB.top); ObjList1(LSB.top); ObjList2(LSB.top);
|
||||
WriteString("endmodule"); WriteLn;
|
||||
Files.Register(F); Texts.WriteString(W, " done"); Texts.WriteLn(W); Texts.Append(Oberon.Log, W.buf)
|
||||
END
|
||||
END List;
|
||||
|
||||
BEGIN Texts.OpenWriter(W); Constructor := Constructor0;
|
||||
C[LSB.const] := "CONST"; C[LSB.typ] := "TYPE"; C[LSB.var] := "VAR";
|
||||
C[LSB.lit] := "LIT"; C[LSB.sel] := "SEL"; C[LSB.range] := ":"; C[LSB.cons] := ",";
|
||||
C[LSB.or] := " | "; C[LSB.xor] := " ^ "; C[LSB.and] := " & "; C[LSB.not] := "~";
|
||||
C[LSB.add] := " + "; C[LSB.sub] := " - "; C[LSB.mul] := " * "; C[LSB.div] := " / ";
|
||||
C[LSB.eql] := " == "; C[LSB.neq] := " != "; C[LSB.lss] := " < "; C[LSB.geq] := " >= "; C[LSB.leq] := " <= "; C[LSB.gtr] := " > ";
|
||||
C[LSB.then] := " ? "; C[LSB.else] := " : "; C[LSB.ts] := "TS"; C[LSB.next] := "--"
|
||||
END LSV.
|
||||
|
|
|
|||
|
|
@ -1,214 +1,214 @@
|
|||
MODULE RISC5 (IN clk, rst, stallX: BIT; (*NW 26.10.2015*)
|
||||
IN inbus, codebus: WORD;
|
||||
OUT adr: [24] BIT;
|
||||
rd, wr, ben: BIT;
|
||||
outbus: WORD);
|
||||
|
||||
CONST StartAdr = 3FF800H'22;
|
||||
|
||||
TYPE PROM := MODULE (IN clk: BIT;
|
||||
IN adr: [9] BIT;
|
||||
OUT data: WORD) ^;
|
||||
|
||||
Multiplier := MODULE (IN clk, run, u: BIT;
|
||||
OUT stall: BIT;
|
||||
IN x, y: WORD;
|
||||
OUT z: [64] BIT) ^;
|
||||
|
||||
Divider := MODULE (IN clk, run, u: BIT;
|
||||
OUT stall: BIT;
|
||||
IN x, y: WORD;
|
||||
OUT quot, rem: WORD) ^;
|
||||
|
||||
FPAdder := MODULE (IN clk, run, u, v: BIT; OUT stall: BIT;
|
||||
IN x, y: WORD; OUT z: WORD) ^;
|
||||
|
||||
FPMultiplier := MODULE (IN clk, run: BIT; OUT stall: BIT;
|
||||
IN x, y: WORD; OUT z: WORD) ^;
|
||||
|
||||
FPDivider := MODULE (IN clk, run: BIT; OUT stall: BIT;
|
||||
IN x, y: WORD; OUT z: WORD) ^;
|
||||
|
||||
REG (clk) PC: [22] BIT; (*program counter*)
|
||||
IR: WORD; (*instruction register*)
|
||||
N, Z, C, OV: BIT; (*condition flags*)
|
||||
stall1, PMsel: BIT;
|
||||
R: [16] WORD; (*data registers*)
|
||||
H: WORD; (*auxiliary register*)
|
||||
|
||||
VAR PM: PROM; (*mem for boot loader*)
|
||||
mulUnit: Multiplier;
|
||||
divUnit: Divider;
|
||||
faddUnit: FPAdder;
|
||||
fmulUnit: FPMultiplier;
|
||||
fdivUnit: FPDivider;
|
||||
|
||||
pcmux, nxpc: [22] BIT;
|
||||
cond, S: BIT;
|
||||
sa, sb, sc: BIT;
|
||||
|
||||
ins, pmout: WORD;
|
||||
p, q, u, v, w: BIT; (*instruction fields*)
|
||||
op, ira, ira0, irb, irc: [4] BIT;
|
||||
cc: [3] BIT;
|
||||
imm: [16] BIT;
|
||||
off: [20] BIT;
|
||||
offL: [24] BIT;
|
||||
|
||||
regwr, stall, stallL, stallM, stallD, stallFA, stallFM, stallFD: BIT;
|
||||
sc1, sc0: [2] BIT; (*shift counts*)
|
||||
|
||||
a0, a1, a2, a3: BIT;
|
||||
inbusL, outbusB0, outbusB1, outbusB2, outbusB3: BYTE;
|
||||
inbusH: [24] BIT;
|
||||
|
||||
A, B, C0, C1, aluRes, regmux: WORD;
|
||||
s1, s2, s3, t1, t2, t3: WORD; (*shifting*)
|
||||
quotient, remainder: WORD;
|
||||
product: [64] BIT;
|
||||
fsum, fprod, fquot: WORD;
|
||||
|
||||
Add, Sub, Mul, Div: BIT;
|
||||
Fadd, Fsub, Fmul, Fdiv: BIT;
|
||||
Ldr, Str, Br: BIT;
|
||||
|
||||
BEGIN PM(clk, pcmux[8:0], pmout);
|
||||
mulUnit (clk, Mul, ~u, stallM, B, C1, product);
|
||||
divUnit (clk, Div, ~u, stallD, B, C1, quotient, remainder);
|
||||
faddUnit (clk, Fadd|Fsub, u, v, stallFA, B, {Fsub^C0.31, C0[30:0]}, fsum);
|
||||
fmulUnit (clk, Fmul, stallFM, B, C0, fprod);
|
||||
fdivUnit (clk, Fdiv, stallFD, B, C0, fquot);
|
||||
|
||||
ins := PMsel -> pmout : IR; (*current instruction*)
|
||||
p := ins.31; (*instruction fields*)
|
||||
q := ins.30;
|
||||
u := ins.29;
|
||||
v := ins.28;
|
||||
w := ins.16;
|
||||
cc:= ins[26:24];
|
||||
ira := ins[27:24];
|
||||
irb := ins[23:20];
|
||||
op := ins[19:16];
|
||||
irc := ins[3:0];
|
||||
imm := ins[15:0]; (*reg instr*)
|
||||
off := ins[19:0]; (*mem instr*)
|
||||
offL := ins[23:0]; (*branch instr*)
|
||||
|
||||
Add := ~p & (op = 8);
|
||||
Sub := ~p & (op = 9);
|
||||
Mul := ~p & (op = 10);
|
||||
Div := ~p & (op = 11);
|
||||
Fadd := ~p & (op = 12);
|
||||
Fsub := ~p & (op = 13);
|
||||
Fmul := ~p & (op = 14);
|
||||
Fdiv := ~p & (op = 15);
|
||||
Ldr := p & ~q & ~u;
|
||||
Str := p & ~q & u;
|
||||
Br := p & q;
|
||||
|
||||
(*ALU*)
|
||||
A := R[ira0]; (*main data path*)
|
||||
B := R[irb];
|
||||
C0 := R[irc];
|
||||
C1 := q -> {v!16, imm} : C0 ;
|
||||
ira0 := Br -> 15'4 : ira;
|
||||
adr := stallL -> B[23:0] + {0'4, off} : {pcmux, 0'2};
|
||||
rd := Ldr & ~stallX & ~stall1;
|
||||
wr := Str & ~stallX & ~stall1;
|
||||
ben := p & ~q & v & ~stallX & ~stall1; (*byte enable*)
|
||||
|
||||
sc0 := C1[1:0];
|
||||
sc1 := C1[3:2];
|
||||
|
||||
(*right shifter*)
|
||||
s1 := (sc0 = 3) -> {(w -> B[2:0] : {B.31 ! 3}), B[31:3]} :
|
||||
(sc0 = 2) -> {(w -> B[1:0] : {B.31 ! 2}), B[31:2]} :
|
||||
(sc0 = 1) -> {(w -> B.0 : B.31), B[31:1]} : B;
|
||||
s2 := (sc1 = 3) -> {(w -> s1[11:0] : {B.31 ! 12}), s1[31:12]} :
|
||||
(sc1 = 2) -> {(w -> s1[7:0] : {B.31 ! 8}), s1[31:8]} :
|
||||
(sc1 = 1) -> {(w -> s1[3:0] : {B.31 ! 4}), s1[31:4]} : s1;
|
||||
s3 := C1.4 -> {(w -> s2[15:0] : {s2.31 ! 16}), s2[31:16]} : s2;
|
||||
|
||||
(*left shifter*)
|
||||
t1 := (sc0 = 3) -> {B[28:0], 0'3} :
|
||||
(sc0 = 2) -> {B[29:0], 0'2} :
|
||||
(sc0 = 1) -> {B[30:0], 0'1} : B;
|
||||
t2 := (sc1 = 3) -> {t1[19:0], 0'12} :
|
||||
(sc1 = 2) -> {t1[23:0], 0'8} :
|
||||
(sc1 = 1) -> {t1[27:0], 0'4} : t1;
|
||||
t3 := C1.4 -> {t2[15:0], 0'16} : t2;
|
||||
|
||||
aluRes :=
|
||||
~op.3 ->
|
||||
(~op.2 ->
|
||||
(~op.1 ->
|
||||
(~op.0 -> (*Mov*)
|
||||
(q ->
|
||||
(~u -> {v!16 , imm} : {imm, 0'16}) :
|
||||
(~u -> C0 : (~v -> H : {N, Z, C, OV, 0'20, 58H'8}))) :
|
||||
t3 ): (*Lsl*)
|
||||
s3) : (*Asr, Ror*)
|
||||
(~op.1 ->
|
||||
(~op.0 -> B & C1 : B & ~C1) : (*And, Ann*)
|
||||
(~op.0 -> B | C1 : B ^ C1)) ): (*Ior, Xor*)
|
||||
(~op.2 ->
|
||||
(~op.1 ->
|
||||
(~op.0 -> B + C + (u&C) : B - C1 - (u&C)) : (*Add, Sub*)
|
||||
(~op.0 -> product[31:0] : quotient)) : (*Mul, Div*)
|
||||
(~op.1 ->
|
||||
fsum : (*Fad, Fsb*)
|
||||
(~op.0 -> fprod : fquot))) ; (*Fml, Fdv*)
|
||||
|
||||
regwr := ~p & ~stall | (Ldr & ~stallX & ~stall1) | (Br & cond & v & ~stallX);
|
||||
a0 := ~adr.1 & ~adr.0;
|
||||
a1 := ~adr.1 & adr.0;
|
||||
a2 := adr.1 & ~adr.0;
|
||||
a3 := adr.1 & adr.0;
|
||||
inbusL := (~ben | a0) -> inbus[7:0] : a1 -> inbus[15:8] : a2 -> inbus[23:16] : inbus[31:24];
|
||||
inbusH := ~ben -> inbus[31:8] : 0'24;
|
||||
regmux := Ldr -> {inbusH, inbusL} : (Br & v) -> {0'8, nxpc, 0'2} : aluRes ;
|
||||
|
||||
outbusB0 := A[7:0];
|
||||
outbusB1 := ben & a1 -> A[7:0] : A[15:8];
|
||||
outbusB2 := ben & a2 -> A[7:0] : A[23:16];
|
||||
outbusB3 := ben & a3 -> A[7:0] : A[31:24];
|
||||
outbus := {outbusB3, outbusB2, outbusB1, outbusB0};
|
||||
|
||||
(*control unit*)
|
||||
S := N ^ OV;
|
||||
nxpc := PC + 1;
|
||||
cond := ins.27 ^ (
|
||||
(cc = 0) & N | (*MI, PL*)
|
||||
(cc = 1) & Z | (*EQ, NE*)
|
||||
(cc = 2) & C | (*CS, CC*)
|
||||
(cc = 3) & OV | (*VS, VC*)
|
||||
(cc = 4) & (C|Z) | (*LS, HI*)
|
||||
(cc = 5) & S | (*LT, GE*)
|
||||
(cc = 6) & (S|Z) | (*LE, GT*)
|
||||
(cc = 7));
|
||||
pcmux := ~rst -> 3FF800H'22 :
|
||||
stall -> PC :
|
||||
(Br & cond & u) -> offL[21:0] + nxpc :
|
||||
(Br & cond & ~u) -> C0[23:2] : nxpc;
|
||||
|
||||
sa := aluRes.31;
|
||||
sb := B.31;
|
||||
sc := C1.31;
|
||||
|
||||
stall := stallL | stallM | stallD | stallFA | stallFM | stallFD | stallX;
|
||||
stallL := (Ldr | Str) & ~stall1;
|
||||
|
||||
(*assignments to registers*)
|
||||
PC := pcmux;
|
||||
PMsel := ~rst | (pcmux[21:12] = 03FFH'10);
|
||||
IR := stall -> IR : codebus;
|
||||
stall1 := stallX -> stall1 : stallL;
|
||||
R[ira0] := regwr -> regmux : A;
|
||||
N := regwr -> regmux.31 : N;
|
||||
Z := regwr -> (regmux = 0) : Z;
|
||||
C := Add -> (sb&sc) | (~sa&~sb&sc) | (~sa&sb&~sc&sa) :
|
||||
Sub -> (~sb&sc) | (sa&~sb&~sc) | (sa&sb&sc) : C;
|
||||
OV := Add -> (sa&~sb&~sc) | (~sa&sb&sc) :
|
||||
Sub -> (sa&~sb&sc) | (~sa&sb&~sc) : OV;
|
||||
H := Mul -> product[63:32] : Div -> remainder : H
|
||||
END RISC5.
|
||||
MODULE RISC5 (IN clk, rst, stallX: BIT; (*NW 26.10.2015*)
|
||||
IN inbus, codebus: WORD;
|
||||
OUT adr: [24] BIT;
|
||||
rd, wr, ben: BIT;
|
||||
outbus: WORD);
|
||||
|
||||
CONST StartAdr = 3FF800H'22;
|
||||
|
||||
TYPE PROM := MODULE (IN clk: BIT;
|
||||
IN adr: [9] BIT;
|
||||
OUT data: WORD) ^;
|
||||
|
||||
Multiplier := MODULE (IN clk, run, u: BIT;
|
||||
OUT stall: BIT;
|
||||
IN x, y: WORD;
|
||||
OUT z: [64] BIT) ^;
|
||||
|
||||
Divider := MODULE (IN clk, run, u: BIT;
|
||||
OUT stall: BIT;
|
||||
IN x, y: WORD;
|
||||
OUT quot, rem: WORD) ^;
|
||||
|
||||
FPAdder := MODULE (IN clk, run, u, v: BIT; OUT stall: BIT;
|
||||
IN x, y: WORD; OUT z: WORD) ^;
|
||||
|
||||
FPMultiplier := MODULE (IN clk, run: BIT; OUT stall: BIT;
|
||||
IN x, y: WORD; OUT z: WORD) ^;
|
||||
|
||||
FPDivider := MODULE (IN clk, run: BIT; OUT stall: BIT;
|
||||
IN x, y: WORD; OUT z: WORD) ^;
|
||||
|
||||
REG (clk) PC: [22] BIT; (*program counter*)
|
||||
IR: WORD; (*instruction register*)
|
||||
N, Z, C, OV: BIT; (*condition flags*)
|
||||
stall1, PMsel: BIT;
|
||||
R: [16] WORD; (*data registers*)
|
||||
H: WORD; (*auxiliary register*)
|
||||
|
||||
VAR PM: PROM; (*mem for boot loader*)
|
||||
mulUnit: Multiplier;
|
||||
divUnit: Divider;
|
||||
faddUnit: FPAdder;
|
||||
fmulUnit: FPMultiplier;
|
||||
fdivUnit: FPDivider;
|
||||
|
||||
pcmux, nxpc: [22] BIT;
|
||||
cond, S: BIT;
|
||||
sa, sb, sc: BIT;
|
||||
|
||||
ins, pmout: WORD;
|
||||
p, q, u, v, w: BIT; (*instruction fields*)
|
||||
op, ira, ira0, irb, irc: [4] BIT;
|
||||
cc: [3] BIT;
|
||||
imm: [16] BIT;
|
||||
off: [20] BIT;
|
||||
offL: [24] BIT;
|
||||
|
||||
regwr, stall, stallL, stallM, stallD, stallFA, stallFM, stallFD: BIT;
|
||||
sc1, sc0: [2] BIT; (*shift counts*)
|
||||
|
||||
a0, a1, a2, a3: BIT;
|
||||
inbusL, outbusB0, outbusB1, outbusB2, outbusB3: BYTE;
|
||||
inbusH: [24] BIT;
|
||||
|
||||
A, B, C0, C1, aluRes, regmux: WORD;
|
||||
s1, s2, s3, t1, t2, t3: WORD; (*shifting*)
|
||||
quotient, remainder: WORD;
|
||||
product: [64] BIT;
|
||||
fsum, fprod, fquot: WORD;
|
||||
|
||||
Add, Sub, Mul, Div: BIT;
|
||||
Fadd, Fsub, Fmul, Fdiv: BIT;
|
||||
Ldr, Str, Br: BIT;
|
||||
|
||||
BEGIN PM(clk, pcmux[8:0], pmout);
|
||||
mulUnit (clk, Mul, ~u, stallM, B, C1, product);
|
||||
divUnit (clk, Div, ~u, stallD, B, C1, quotient, remainder);
|
||||
faddUnit (clk, Fadd|Fsub, u, v, stallFA, B, {Fsub^C0.31, C0[30:0]}, fsum);
|
||||
fmulUnit (clk, Fmul, stallFM, B, C0, fprod);
|
||||
fdivUnit (clk, Fdiv, stallFD, B, C0, fquot);
|
||||
|
||||
ins := PMsel -> pmout : IR; (*current instruction*)
|
||||
p := ins.31; (*instruction fields*)
|
||||
q := ins.30;
|
||||
u := ins.29;
|
||||
v := ins.28;
|
||||
w := ins.16;
|
||||
cc:= ins[26:24];
|
||||
ira := ins[27:24];
|
||||
irb := ins[23:20];
|
||||
op := ins[19:16];
|
||||
irc := ins[3:0];
|
||||
imm := ins[15:0]; (*reg instr*)
|
||||
off := ins[19:0]; (*mem instr*)
|
||||
offL := ins[23:0]; (*branch instr*)
|
||||
|
||||
Add := ~p & (op = 8);
|
||||
Sub := ~p & (op = 9);
|
||||
Mul := ~p & (op = 10);
|
||||
Div := ~p & (op = 11);
|
||||
Fadd := ~p & (op = 12);
|
||||
Fsub := ~p & (op = 13);
|
||||
Fmul := ~p & (op = 14);
|
||||
Fdiv := ~p & (op = 15);
|
||||
Ldr := p & ~q & ~u;
|
||||
Str := p & ~q & u;
|
||||
Br := p & q;
|
||||
|
||||
(*ALU*)
|
||||
A := R[ira0]; (*main data path*)
|
||||
B := R[irb];
|
||||
C0 := R[irc];
|
||||
C1 := q -> {v!16, imm} : C0 ;
|
||||
ira0 := Br -> 15'4 : ira;
|
||||
adr := stallL -> B[23:0] + {0'4, off} : {pcmux, 0'2};
|
||||
rd := Ldr & ~stallX & ~stall1;
|
||||
wr := Str & ~stallX & ~stall1;
|
||||
ben := p & ~q & v & ~stallX & ~stall1; (*byte enable*)
|
||||
|
||||
sc0 := C1[1:0];
|
||||
sc1 := C1[3:2];
|
||||
|
||||
(*right shifter*)
|
||||
s1 := (sc0 = 3) -> {(w -> B[2:0] : {B.31 ! 3}), B[31:3]} :
|
||||
(sc0 = 2) -> {(w -> B[1:0] : {B.31 ! 2}), B[31:2]} :
|
||||
(sc0 = 1) -> {(w -> B.0 : B.31), B[31:1]} : B;
|
||||
s2 := (sc1 = 3) -> {(w -> s1[11:0] : {B.31 ! 12}), s1[31:12]} :
|
||||
(sc1 = 2) -> {(w -> s1[7:0] : {B.31 ! 8}), s1[31:8]} :
|
||||
(sc1 = 1) -> {(w -> s1[3:0] : {B.31 ! 4}), s1[31:4]} : s1;
|
||||
s3 := C1.4 -> {(w -> s2[15:0] : {s2.31 ! 16}), s2[31:16]} : s2;
|
||||
|
||||
(*left shifter*)
|
||||
t1 := (sc0 = 3) -> {B[28:0], 0'3} :
|
||||
(sc0 = 2) -> {B[29:0], 0'2} :
|
||||
(sc0 = 1) -> {B[30:0], 0'1} : B;
|
||||
t2 := (sc1 = 3) -> {t1[19:0], 0'12} :
|
||||
(sc1 = 2) -> {t1[23:0], 0'8} :
|
||||
(sc1 = 1) -> {t1[27:0], 0'4} : t1;
|
||||
t3 := C1.4 -> {t2[15:0], 0'16} : t2;
|
||||
|
||||
aluRes :=
|
||||
~op.3 ->
|
||||
(~op.2 ->
|
||||
(~op.1 ->
|
||||
(~op.0 -> (*Mov*)
|
||||
(q ->
|
||||
(~u -> {v!16 , imm} : {imm, 0'16}) :
|
||||
(~u -> C0 : (~v -> H : {N, Z, C, OV, 0'20, 58H'8}))) :
|
||||
t3 ): (*Lsl*)
|
||||
s3) : (*Asr, Ror*)
|
||||
(~op.1 ->
|
||||
(~op.0 -> B & C1 : B & ~C1) : (*And, Ann*)
|
||||
(~op.0 -> B | C1 : B ^ C1)) ): (*Ior, Xor*)
|
||||
(~op.2 ->
|
||||
(~op.1 ->
|
||||
(~op.0 -> B + C + (u&C) : B - C1 - (u&C)) : (*Add, Sub*)
|
||||
(~op.0 -> product[31:0] : quotient)) : (*Mul, Div*)
|
||||
(~op.1 ->
|
||||
fsum : (*Fad, Fsb*)
|
||||
(~op.0 -> fprod : fquot))) ; (*Fml, Fdv*)
|
||||
|
||||
regwr := ~p & ~stall | (Ldr & ~stallX & ~stall1) | (Br & cond & v & ~stallX);
|
||||
a0 := ~adr.1 & ~adr.0;
|
||||
a1 := ~adr.1 & adr.0;
|
||||
a2 := adr.1 & ~adr.0;
|
||||
a3 := adr.1 & adr.0;
|
||||
inbusL := (~ben | a0) -> inbus[7:0] : a1 -> inbus[15:8] : a2 -> inbus[23:16] : inbus[31:24];
|
||||
inbusH := ~ben -> inbus[31:8] : 0'24;
|
||||
regmux := Ldr -> {inbusH, inbusL} : (Br & v) -> {0'8, nxpc, 0'2} : aluRes ;
|
||||
|
||||
outbusB0 := A[7:0];
|
||||
outbusB1 := ben & a1 -> A[7:0] : A[15:8];
|
||||
outbusB2 := ben & a2 -> A[7:0] : A[23:16];
|
||||
outbusB3 := ben & a3 -> A[7:0] : A[31:24];
|
||||
outbus := {outbusB3, outbusB2, outbusB1, outbusB0};
|
||||
|
||||
(*control unit*)
|
||||
S := N ^ OV;
|
||||
nxpc := PC + 1;
|
||||
cond := ins.27 ^ (
|
||||
(cc = 0) & N | (*MI, PL*)
|
||||
(cc = 1) & Z | (*EQ, NE*)
|
||||
(cc = 2) & C | (*CS, CC*)
|
||||
(cc = 3) & OV | (*VS, VC*)
|
||||
(cc = 4) & (C|Z) | (*LS, HI*)
|
||||
(cc = 5) & S | (*LT, GE*)
|
||||
(cc = 6) & (S|Z) | (*LE, GT*)
|
||||
(cc = 7));
|
||||
pcmux := ~rst -> 3FF800H'22 :
|
||||
stall -> PC :
|
||||
(Br & cond & u) -> offL[21:0] + nxpc :
|
||||
(Br & cond & ~u) -> C0[23:2] : nxpc;
|
||||
|
||||
sa := aluRes.31;
|
||||
sb := B.31;
|
||||
sc := C1.31;
|
||||
|
||||
stall := stallL | stallM | stallD | stallFA | stallFM | stallFD | stallX;
|
||||
stallL := (Ldr | Str) & ~stall1;
|
||||
|
||||
(*assignments to registers*)
|
||||
PC := pcmux;
|
||||
PMsel := ~rst | (pcmux[21:12] = 03FFH'10);
|
||||
IR := stall -> IR : codebus;
|
||||
stall1 := stallX -> stall1 : stallL;
|
||||
R[ira0] := regwr -> regmux : A;
|
||||
N := regwr -> regmux.31 : N;
|
||||
Z := regwr -> (regmux = 0) : Z;
|
||||
C := Add -> (sb&sc) | (~sa&~sb&sc) | (~sa&sb&~sc&sa) :
|
||||
Sub -> (~sb&sc) | (sa&~sb&~sc) | (sa&sb&sc) : C;
|
||||
OV := Add -> (sa&~sb&~sc) | (~sa&sb&sc) :
|
||||
Sub -> (sa&~sb&sc) | (~sa&sb&~sc) : OV;
|
||||
H := Mul -> product[63:32] : Div -> remainder : H
|
||||
END RISC5.
|
||||
|
|
|
|||
|
|
@ -1,113 +1,113 @@
|
|||
`timescale 1ns / 1 ps
|
||||
module RISC5( // translated from Lola
|
||||
input clk, rst, stallX,
|
||||
input [31:0] inbus, codebus,
|
||||
output [23:0] adr,
|
||||
output rd, wr, ben,
|
||||
output [31:0] outbus);
|
||||
reg [21:0] PC;
|
||||
reg [31:0] IR;
|
||||
reg N, Z, C, OV, stall1, PMsel;
|
||||
reg [31:0] R[15:0];
|
||||
reg [31:0] H;
|
||||
wire [21:0] pcmux, nxpc;
|
||||
wire cond, S, sa, sb, sc;
|
||||
wire [31:0] ins, pmout;
|
||||
wire p, q, u, v, w;
|
||||
wire [3:0] op, ira, ira0, irb, irc;
|
||||
wire [2:0] cc;
|
||||
wire [15:0] imm;
|
||||
wire [19:0] off;
|
||||
wire [23:0] offL;
|
||||
wire regwr, stall, stallL, stallM, stallD, stallFA, stallFM, stallFD;
|
||||
wire [1:0] sc1, sc0;
|
||||
wire a0, a1, a2, a3;
|
||||
wire [7:0] inbusL, outbusB0, outbusB1, outbusB2, outbusB3;
|
||||
wire [23:0] inbusH;
|
||||
wire [31:0] A, B, C0, C1, aluRes, regmux, s1, s2, s3, t1, t2, t3, quotient, remainder;
|
||||
wire [63:0] product;
|
||||
wire [31:0] fsum, fprod, fquot;
|
||||
wire Add, Sub, Mul, Div, Fadd, Fsub, Fmul, Fdiv, Ldr, Str, Br;
|
||||
assign adr = stallL ? (B[23:0] + {4'h0, off}) : {pcmux, 2'h0};
|
||||
assign rd = ((Ldr & ~stallX) & ~stall1);
|
||||
assign wr = ((Str & ~stallX) & ~stall1);
|
||||
assign ben = ((((p & ~q) & v) & ~stallX) & ~stall1);
|
||||
assign outbus = {outbusB3, outbusB2, outbusB1, outbusB0};
|
||||
PROM PM(.clk(clk), .adr(pcmux[8:0]), .data(pmout));
|
||||
Multiplier mulUnit(.clk(clk), .run(Mul), .u(~u), .stall(stallM), .x(B), .y(C1), .z(product));
|
||||
Divider divUnit(.clk(clk), .run(Div), .u(~u), .stall(stallD), .x(B), .y(C1), .quot(quotient), .rem(remainder));
|
||||
FPAdder faddUnit(.clk(clk), .run((Fadd | Fsub)), .u(u), .v(v), .stall(stallFA), .x(B), .y({(Fsub ^ C0[31]), C0[30:0]}), .z(fsum));
|
||||
FPMultiplier fmulUnit(.clk(clk), .run(Fmul), .stall(stallFM), .x(B), .y(C0), .z(fprod));
|
||||
FPDivider fdivUnit(.clk(clk), .run(Fdiv), .stall(stallFD), .x(B), .y(C0), .z(fquot));
|
||||
assign pcmux = ~rst ? 22'h3FF800 : stall ? PC : ((Br & cond) & u) ? (offL[21:0] + nxpc) : ((Br & cond) & ~u) ? C0[23:2] : nxpc;
|
||||
assign nxpc = (PC + 1);
|
||||
assign cond = (ins[27] ^ (((((((((cc == 0) & N) | ((cc == 1) & Z)) | ((cc == 2) & C)) | ((cc == 3) & OV)) | ((cc == 4) & (C | Z))) | ((cc == 5) & S)) | ((cc == 6) & (S | Z))) | (cc == 7)));
|
||||
assign S = (N ^ OV);
|
||||
assign sa = aluRes[31];
|
||||
assign sb = B[31];
|
||||
assign sc = C1[31];
|
||||
assign ins = PMsel ? pmout : IR;
|
||||
assign p = ins[31];
|
||||
assign q = ins[30];
|
||||
assign u = ins[29];
|
||||
assign v = ins[28];
|
||||
assign w = ins[16];
|
||||
assign op = ins[19:16];
|
||||
assign ira = ins[27:24];
|
||||
assign ira0 = Br ? 4'hF : ira;
|
||||
assign irb = ins[23:20];
|
||||
assign irc = ins[3:0];
|
||||
assign cc = ins[26:24];
|
||||
assign imm = ins[15:0];
|
||||
assign off = ins[19:0];
|
||||
assign offL = ins[23:0];
|
||||
assign regwr = (((~p & ~stall) | ((Ldr & ~stallX) & ~stall1)) | (((Br & cond) & v) & ~stallX));
|
||||
assign stall = ((((((stallL | stallM) | stallD) | stallFA) | stallFM) | stallFD) | stallX);
|
||||
assign stallL = ((Ldr | Str) & ~stall1);
|
||||
assign sc1 = C1[3:2];
|
||||
assign sc0 = C1[1:0];
|
||||
assign a0 = (~adr[1] & ~adr[0]);
|
||||
assign a1 = (~adr[1] & adr[0]);
|
||||
assign a2 = (adr[1] & ~adr[0]);
|
||||
assign a3 = (adr[1] & adr[0]);
|
||||
assign inbusL = (~ben | a0) ? inbus[7:0] : a1 ? inbus[15:8] : a2 ? inbus[23:16] : inbus[31:24];
|
||||
assign outbusB0 = A[7:0];
|
||||
assign outbusB1 = (ben & a1) ? A[7:0] : A[15:8];
|
||||
assign outbusB2 = (ben & a2) ? A[7:0] : A[23:16];
|
||||
assign outbusB3 = (ben & a3) ? A[7:0] : A[31:24];
|
||||
assign inbusH = ~ben ? inbus[31:8] : 24'h0;
|
||||
assign A = R[ira0];
|
||||
assign B = R[irb];
|
||||
assign C0 = R[irc];
|
||||
assign C1 = q ? {{16{v}}, imm} : C0;
|
||||
assign aluRes = ~op[3] ? ~op[2] ? ~op[1] ? ~op[0] ? q ? ~u ? {{16{v}}, imm} : {imm, 16'h0} : ~u ? C0 : ~v ? H : {N, Z, C, OV, 20'h0, 8'h58} : t3 : s3 : ~op[1] ? ~op[0] ? (B & C1) : (B & ~C1) : ~op[0] ? (B | C1) : (B ^ C1) : ~op[2] ? ~op[1] ? ~op[0] ? ((B + C) + (u & C)) : ((B - C1) - (u & C)) : ~op[0] ? product[31:0] : quotient : ~op[1] ? fsum : ~op[0] ? fprod : fquot;
|
||||
assign regmux = Ldr ? {inbusH, inbusL} : (Br & v) ? {8'h0, nxpc, 2'h0} : aluRes;
|
||||
assign s1 = (sc0 == 3) ? {w ? B[2:0] : {3{B[31]}}, B[31:3]} : (sc0 == 2) ? {w ? B[1:0] : {2{B[31]}}, B[31:2]} : (sc0 == 1) ? {w ? B[0] : B[31], B[31:1]} : B;
|
||||
assign s2 = (sc1 == 3) ? {w ? s1[11:0] : {12{B[31]}}, s1[31:12]} : (sc1 == 2) ? {w ? s1[7:0] : {8{B[31]}}, s1[31:8]} : (sc1 == 1) ? {w ? s1[3:0] : {4{B[31]}}, s1[31:4]} : s1;
|
||||
assign s3 = C1[4] ? {w ? s2[15:0] : {16{s2[31]}}, s2[31:16]} : s2;
|
||||
assign t1 = (sc0 == 3) ? {B[28:0], 3'h0} : (sc0 == 2) ? {B[29:0], 2'h0} : (sc0 == 1) ? {B[30:0], 1'h0} : B;
|
||||
assign t2 = (sc1 == 3) ? {t1[19:0], 12'h0} : (sc1 == 2) ? {t1[23:0], 8'h0} : (sc1 == 1) ? {t1[27:0], 4'h0} : t1;
|
||||
assign t3 = C1[4] ? {t2[15:0], 16'h0} : t2;
|
||||
assign Add = (~p & (op == 8));
|
||||
assign Sub = (~p & (op == 9));
|
||||
assign Mul = (~p & (op == 10));
|
||||
assign Div = (~p & (op == 11));
|
||||
assign Fadd = (~p & (op == 12));
|
||||
assign Fsub = (~p & (op == 13));
|
||||
assign Fmul = (~p & (op == 14));
|
||||
assign Fdiv = (~p & (op == 15));
|
||||
assign Ldr = ((p & ~q) & ~u);
|
||||
assign Str = ((p & ~q) & u);
|
||||
assign Br = (p & q);
|
||||
always @ (posedge clk) begin PC <= pcmux;
|
||||
IR <= stall ? IR : codebus;
|
||||
N <= regwr ? regmux[31] : N;
|
||||
Z <= regwr ? (regmux == 0) : Z;
|
||||
C <= Add ? (((sb & sc) | ((~sa & ~sb) & sc)) | (((~sa & sb) & ~sc) & sa)) : Sub ? (((~sb & sc) | ((sa & ~sb) & ~sc)) | ((sa & sb) & sc)) : C;
|
||||
OV <= Add ? (((sa & ~sb) & ~sc) | ((~sa & sb) & sc)) : Sub ? (((sa & ~sb) & sc) | ((~sa & sb) & ~sc)) : OV;
|
||||
stall1 <= stallX ? stall1 : stallL;
|
||||
PMsel <= (~rst | (pcmux[21:12] == 10'h3FF));
|
||||
R[ira0] <= regwr ? regmux : A;
|
||||
H <= Mul ? product[63:32] : Div ? remainder : H;
|
||||
end
|
||||
endmodule
|
||||
`timescale 1ns / 1 ps
|
||||
module RISC5( // translated from Lola
|
||||
input clk, rst, stallX,
|
||||
input [31:0] inbus, codebus,
|
||||
output [23:0] adr,
|
||||
output rd, wr, ben,
|
||||
output [31:0] outbus);
|
||||
reg [21:0] PC;
|
||||
reg [31:0] IR;
|
||||
reg N, Z, C, OV, stall1, PMsel;
|
||||
reg [31:0] R[15:0];
|
||||
reg [31:0] H;
|
||||
wire [21:0] pcmux, nxpc;
|
||||
wire cond, S, sa, sb, sc;
|
||||
wire [31:0] ins, pmout;
|
||||
wire p, q, u, v, w;
|
||||
wire [3:0] op, ira, ira0, irb, irc;
|
||||
wire [2:0] cc;
|
||||
wire [15:0] imm;
|
||||
wire [19:0] off;
|
||||
wire [23:0] offL;
|
||||
wire regwr, stall, stallL, stallM, stallD, stallFA, stallFM, stallFD;
|
||||
wire [1:0] sc1, sc0;
|
||||
wire a0, a1, a2, a3;
|
||||
wire [7:0] inbusL, outbusB0, outbusB1, outbusB2, outbusB3;
|
||||
wire [23:0] inbusH;
|
||||
wire [31:0] A, B, C0, C1, aluRes, regmux, s1, s2, s3, t1, t2, t3, quotient, remainder;
|
||||
wire [63:0] product;
|
||||
wire [31:0] fsum, fprod, fquot;
|
||||
wire Add, Sub, Mul, Div, Fadd, Fsub, Fmul, Fdiv, Ldr, Str, Br;
|
||||
assign adr = stallL ? (B[23:0] + {4'h0, off}) : {pcmux, 2'h0};
|
||||
assign rd = ((Ldr & ~stallX) & ~stall1);
|
||||
assign wr = ((Str & ~stallX) & ~stall1);
|
||||
assign ben = ((((p & ~q) & v) & ~stallX) & ~stall1);
|
||||
assign outbus = {outbusB3, outbusB2, outbusB1, outbusB0};
|
||||
PROM PM(.clk(clk), .adr(pcmux[8:0]), .data(pmout));
|
||||
Multiplier mulUnit(.clk(clk), .run(Mul), .u(~u), .stall(stallM), .x(B), .y(C1), .z(product));
|
||||
Divider divUnit(.clk(clk), .run(Div), .u(~u), .stall(stallD), .x(B), .y(C1), .quot(quotient), .rem(remainder));
|
||||
FPAdder faddUnit(.clk(clk), .run((Fadd | Fsub)), .u(u), .v(v), .stall(stallFA), .x(B), .y({(Fsub ^ C0[31]), C0[30:0]}), .z(fsum));
|
||||
FPMultiplier fmulUnit(.clk(clk), .run(Fmul), .stall(stallFM), .x(B), .y(C0), .z(fprod));
|
||||
FPDivider fdivUnit(.clk(clk), .run(Fdiv), .stall(stallFD), .x(B), .y(C0), .z(fquot));
|
||||
assign pcmux = ~rst ? 22'h3FF800 : stall ? PC : ((Br & cond) & u) ? (offL[21:0] + nxpc) : ((Br & cond) & ~u) ? C0[23:2] : nxpc;
|
||||
assign nxpc = (PC + 1);
|
||||
assign cond = (ins[27] ^ (((((((((cc == 0) & N) | ((cc == 1) & Z)) | ((cc == 2) & C)) | ((cc == 3) & OV)) | ((cc == 4) & (C | Z))) | ((cc == 5) & S)) | ((cc == 6) & (S | Z))) | (cc == 7)));
|
||||
assign S = (N ^ OV);
|
||||
assign sa = aluRes[31];
|
||||
assign sb = B[31];
|
||||
assign sc = C1[31];
|
||||
assign ins = PMsel ? pmout : IR;
|
||||
assign p = ins[31];
|
||||
assign q = ins[30];
|
||||
assign u = ins[29];
|
||||
assign v = ins[28];
|
||||
assign w = ins[16];
|
||||
assign op = ins[19:16];
|
||||
assign ira = ins[27:24];
|
||||
assign ira0 = Br ? 4'hF : ira;
|
||||
assign irb = ins[23:20];
|
||||
assign irc = ins[3:0];
|
||||
assign cc = ins[26:24];
|
||||
assign imm = ins[15:0];
|
||||
assign off = ins[19:0];
|
||||
assign offL = ins[23:0];
|
||||
assign regwr = (((~p & ~stall) | ((Ldr & ~stallX) & ~stall1)) | (((Br & cond) & v) & ~stallX));
|
||||
assign stall = ((((((stallL | stallM) | stallD) | stallFA) | stallFM) | stallFD) | stallX);
|
||||
assign stallL = ((Ldr | Str) & ~stall1);
|
||||
assign sc1 = C1[3:2];
|
||||
assign sc0 = C1[1:0];
|
||||
assign a0 = (~adr[1] & ~adr[0]);
|
||||
assign a1 = (~adr[1] & adr[0]);
|
||||
assign a2 = (adr[1] & ~adr[0]);
|
||||
assign a3 = (adr[1] & adr[0]);
|
||||
assign inbusL = (~ben | a0) ? inbus[7:0] : a1 ? inbus[15:8] : a2 ? inbus[23:16] : inbus[31:24];
|
||||
assign outbusB0 = A[7:0];
|
||||
assign outbusB1 = (ben & a1) ? A[7:0] : A[15:8];
|
||||
assign outbusB2 = (ben & a2) ? A[7:0] : A[23:16];
|
||||
assign outbusB3 = (ben & a3) ? A[7:0] : A[31:24];
|
||||
assign inbusH = ~ben ? inbus[31:8] : 24'h0;
|
||||
assign A = R[ira0];
|
||||
assign B = R[irb];
|
||||
assign C0 = R[irc];
|
||||
assign C1 = q ? {{16{v}}, imm} : C0;
|
||||
assign aluRes = ~op[3] ? ~op[2] ? ~op[1] ? ~op[0] ? q ? ~u ? {{16{v}}, imm} : {imm, 16'h0} : ~u ? C0 : ~v ? H : {N, Z, C, OV, 20'h0, 8'h58} : t3 : s3 : ~op[1] ? ~op[0] ? (B & C1) : (B & ~C1) : ~op[0] ? (B | C1) : (B ^ C1) : ~op[2] ? ~op[1] ? ~op[0] ? ((B + C) + (u & C)) : ((B - C1) - (u & C)) : ~op[0] ? product[31:0] : quotient : ~op[1] ? fsum : ~op[0] ? fprod : fquot;
|
||||
assign regmux = Ldr ? {inbusH, inbusL} : (Br & v) ? {8'h0, nxpc, 2'h0} : aluRes;
|
||||
assign s1 = (sc0 == 3) ? {w ? B[2:0] : {3{B[31]}}, B[31:3]} : (sc0 == 2) ? {w ? B[1:0] : {2{B[31]}}, B[31:2]} : (sc0 == 1) ? {w ? B[0] : B[31], B[31:1]} : B;
|
||||
assign s2 = (sc1 == 3) ? {w ? s1[11:0] : {12{B[31]}}, s1[31:12]} : (sc1 == 2) ? {w ? s1[7:0] : {8{B[31]}}, s1[31:8]} : (sc1 == 1) ? {w ? s1[3:0] : {4{B[31]}}, s1[31:4]} : s1;
|
||||
assign s3 = C1[4] ? {w ? s2[15:0] : {16{s2[31]}}, s2[31:16]} : s2;
|
||||
assign t1 = (sc0 == 3) ? {B[28:0], 3'h0} : (sc0 == 2) ? {B[29:0], 2'h0} : (sc0 == 1) ? {B[30:0], 1'h0} : B;
|
||||
assign t2 = (sc1 == 3) ? {t1[19:0], 12'h0} : (sc1 == 2) ? {t1[23:0], 8'h0} : (sc1 == 1) ? {t1[27:0], 4'h0} : t1;
|
||||
assign t3 = C1[4] ? {t2[15:0], 16'h0} : t2;
|
||||
assign Add = (~p & (op == 8));
|
||||
assign Sub = (~p & (op == 9));
|
||||
assign Mul = (~p & (op == 10));
|
||||
assign Div = (~p & (op == 11));
|
||||
assign Fadd = (~p & (op == 12));
|
||||
assign Fsub = (~p & (op == 13));
|
||||
assign Fmul = (~p & (op == 14));
|
||||
assign Fdiv = (~p & (op == 15));
|
||||
assign Ldr = ((p & ~q) & ~u);
|
||||
assign Str = ((p & ~q) & u);
|
||||
assign Br = (p & q);
|
||||
always @ (posedge clk) begin PC <= pcmux;
|
||||
IR <= stall ? IR : codebus;
|
||||
N <= regwr ? regmux[31] : N;
|
||||
Z <= regwr ? (regmux == 0) : Z;
|
||||
C <= Add ? (((sb & sc) | ((~sa & ~sb) & sc)) | (((~sa & sb) & ~sc) & sa)) : Sub ? (((~sb & sc) | ((sa & ~sb) & ~sc)) | ((sa & sb) & sc)) : C;
|
||||
OV <= Add ? (((sa & ~sb) & ~sc) | ((~sa & sb) & sc)) : Sub ? (((sa & ~sb) & sc) | ((~sa & sb) & ~sc)) : OV;
|
||||
stall1 <= stallX ? stall1 : stallL;
|
||||
PMsel <= (~rst | (pcmux[21:12] == 10'h3FF));
|
||||
R[ira0] <= regwr ? regmux : A;
|
||||
H <= Mul ? product[63:32] : Div ? remainder : H;
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -1,12 +1,12 @@
|
|||
MODULE Lola; (* Command line runner for Lola to verilog compilation *)
|
||||
IMPORT LSB, LSC, LSV, Platform, Console;
|
||||
BEGIN
|
||||
IF Platform.ArgCount < 3 THEN
|
||||
Console.String("Lola - compile lola source to verilog source."); Console.Ln; Console.Ln;
|
||||
Console.String("usage:"); Console.Ln; Console.Ln;
|
||||
Console.String(" lola lola-source-file verilog-source-file"); Console.Ln; Console.Ln;
|
||||
ELSE
|
||||
LSC.Compile;
|
||||
IF LSB.modname # "" THEN LSV.List END
|
||||
END
|
||||
END Lola.
|
||||
MODULE Lola; (* Command line runner for Lola to verilog compilation *)
|
||||
IMPORT LSB, LSC, LSV, Platform, Console;
|
||||
BEGIN
|
||||
IF Platform.ArgCount < 3 THEN
|
||||
Console.String("Lola - compile lola source to verilog source."); Console.Ln; Console.Ln;
|
||||
Console.String("usage:"); Console.Ln; Console.Ln;
|
||||
Console.String(" lola lola-source-file verilog-source-file"); Console.Ln; Console.Ln;
|
||||
ELSE
|
||||
LSC.Compile;
|
||||
IF LSB.modname # "" THEN LSV.List END
|
||||
END
|
||||
END Lola.
|
||||
|
|
|
|||
|
|
@ -1,113 +1,113 @@
|
|||
`timescale 1ns / 1 ps
|
||||
module RISC5( // translated from Lola
|
||||
input clk, rst, stallX,
|
||||
input [31:0] inbus, codebus,
|
||||
output [23:0] adr,
|
||||
output rd, wr, ben,
|
||||
output [31:0] outbus);
|
||||
reg [21:0] PC;
|
||||
reg [31:0] IR;
|
||||
reg N, Z, C, OV, stall1, PMsel;
|
||||
reg [31:0] R[15:0];
|
||||
reg [31:0] H;
|
||||
wire [21:0] pcmux, nxpc;
|
||||
wire cond, S, sa, sb, sc;
|
||||
wire [31:0] ins, pmout;
|
||||
wire p, q, u, v, w;
|
||||
wire [3:0] op, ira, ira0, irb, irc;
|
||||
wire [2:0] cc;
|
||||
wire [15:0] imm;
|
||||
wire [19:0] off;
|
||||
wire [23:0] offL;
|
||||
wire regwr, stall, stallL, stallM, stallD, stallFA, stallFM, stallFD;
|
||||
wire [1:0] sc1, sc0;
|
||||
wire a0, a1, a2, a3;
|
||||
wire [7:0] inbusL, outbusB0, outbusB1, outbusB2, outbusB3;
|
||||
wire [23:0] inbusH;
|
||||
wire [31:0] A, B, C0, C1, aluRes, regmux, s1, s2, s3, t1, t2, t3, quotient, remainder;
|
||||
wire [63:0] product;
|
||||
wire [31:0] fsum, fprod, fquot;
|
||||
wire Add, Sub, Mul, Div, Fadd, Fsub, Fmul, Fdiv, Ldr, Str, Br;
|
||||
assign adr = stallL ? (B[23:0] + {4'h0, off}) : {pcmux, 2'h0};
|
||||
assign rd = ((Ldr & ~stallX) & ~stall1);
|
||||
assign wr = ((Str & ~stallX) & ~stall1);
|
||||
assign ben = ((((p & ~q) & v) & ~stallX) & ~stall1);
|
||||
assign outbus = {outbusB3, outbusB2, outbusB1, outbusB0};
|
||||
PROM PM(.clk(clk), .adr(pcmux[8:0]), .data(pmout));
|
||||
Multiplier mulUnit(.clk(clk), .run(Mul), .u(~u), .stall(stallM), .x(B), .y(C1), .z(product));
|
||||
Divider divUnit(.clk(clk), .run(Div), .u(~u), .stall(stallD), .x(B), .y(C1), .quot(quotient), .rem(remainder));
|
||||
FPAdder faddUnit(.clk(clk), .run((Fadd | Fsub)), .u(u), .v(v), .stall(stallFA), .x(B), .y({(Fsub ^ C0[31]), C0[30:0]}), .z(fsum));
|
||||
FPMultiplier fmulUnit(.clk(clk), .run(Fmul), .stall(stallFM), .x(B), .y(C0), .z(fprod));
|
||||
FPDivider fdivUnit(.clk(clk), .run(Fdiv), .stall(stallFD), .x(B), .y(C0), .z(fquot));
|
||||
assign pcmux = ~rst ? 22'h3FF800 : stall ? PC : ((Br & cond) & u) ? (offL[21:0] + nxpc) : ((Br & cond) & ~u) ? C0[23:2] : nxpc;
|
||||
assign nxpc = (PC + 1);
|
||||
assign cond = (ins[27] ^ (((((((((cc == 0) & N) | ((cc == 1) & Z)) | ((cc == 2) & C)) | ((cc == 3) & OV)) | ((cc == 4) & (C | Z))) | ((cc == 5) & S)) | ((cc == 6) & (S | Z))) | (cc == 7)));
|
||||
assign S = (N ^ OV);
|
||||
assign sa = aluRes[31];
|
||||
assign sb = B[31];
|
||||
assign sc = C1[31];
|
||||
assign ins = PMsel ? pmout : IR;
|
||||
assign p = ins[31];
|
||||
assign q = ins[30];
|
||||
assign u = ins[29];
|
||||
assign v = ins[28];
|
||||
assign w = ins[16];
|
||||
assign op = ins[19:16];
|
||||
assign ira = ins[27:24];
|
||||
assign ira0 = Br ? 4'hF : ira;
|
||||
assign irb = ins[23:20];
|
||||
assign irc = ins[3:0];
|
||||
assign cc = ins[26:24];
|
||||
assign imm = ins[15:0];
|
||||
assign off = ins[19:0];
|
||||
assign offL = ins[23:0];
|
||||
assign regwr = (((~p & ~stall) | ((Ldr & ~stallX) & ~stall1)) | (((Br & cond) & v) & ~stallX));
|
||||
assign stall = ((((((stallL | stallM) | stallD) | stallFA) | stallFM) | stallFD) | stallX);
|
||||
assign stallL = ((Ldr | Str) & ~stall1);
|
||||
assign sc1 = C1[3:2];
|
||||
assign sc0 = C1[1:0];
|
||||
assign a0 = (~adr[1] & ~adr[0]);
|
||||
assign a1 = (~adr[1] & adr[0]);
|
||||
assign a2 = (adr[1] & ~adr[0]);
|
||||
assign a3 = (adr[1] & adr[0]);
|
||||
assign inbusL = (~ben | a0) ? inbus[7:0] : a1 ? inbus[15:8] : a2 ? inbus[23:16] : inbus[31:24];
|
||||
assign outbusB0 = A[7:0];
|
||||
assign outbusB1 = (ben & a1) ? A[7:0] : A[15:8];
|
||||
assign outbusB2 = (ben & a2) ? A[7:0] : A[23:16];
|
||||
assign outbusB3 = (ben & a3) ? A[7:0] : A[31:24];
|
||||
assign inbusH = ~ben ? inbus[31:8] : 24'h0;
|
||||
assign A = R[ira0];
|
||||
assign B = R[irb];
|
||||
assign C0 = R[irc];
|
||||
assign C1 = q ? {{16{v}}, imm} : C0;
|
||||
assign aluRes = ~op[3] ? ~op[2] ? ~op[1] ? ~op[0] ? q ? ~u ? {{16{v}}, imm} : {imm, 16'h0} : ~u ? C0 : ~v ? H : {N, Z, C, OV, 20'h0, 8'h58} : t3 : s3 : ~op[1] ? ~op[0] ? (B & C1) : (B & ~C1) : ~op[0] ? (B | C1) : (B ^ C1) : ~op[2] ? ~op[1] ? ~op[0] ? ((B + C) + (u & C)) : ((B - C1) - (u & C)) : ~op[0] ? product[31:0] : quotient : ~op[1] ? fsum : ~op[0] ? fprod : fquot;
|
||||
assign regmux = Ldr ? {inbusH, inbusL} : (Br & v) ? {8'h0, nxpc, 2'h0} : aluRes;
|
||||
assign s1 = (sc0 == 3) ? {w ? B[2:0] : {3{B[31]}}, B[31:3]} : (sc0 == 2) ? {w ? B[1:0] : {2{B[31]}}, B[31:2]} : (sc0 == 1) ? {w ? B[0] : B[31], B[31:1]} : B;
|
||||
assign s2 = (sc1 == 3) ? {w ? s1[11:0] : {12{B[31]}}, s1[31:12]} : (sc1 == 2) ? {w ? s1[7:0] : {8{B[31]}}, s1[31:8]} : (sc1 == 1) ? {w ? s1[3:0] : {4{B[31]}}, s1[31:4]} : s1;
|
||||
assign s3 = C1[4] ? {w ? s2[15:0] : {16{s2[31]}}, s2[31:16]} : s2;
|
||||
assign t1 = (sc0 == 3) ? {B[28:0], 3'h0} : (sc0 == 2) ? {B[29:0], 2'h0} : (sc0 == 1) ? {B[30:0], 1'h0} : B;
|
||||
assign t2 = (sc1 == 3) ? {t1[19:0], 12'h0} : (sc1 == 2) ? {t1[23:0], 8'h0} : (sc1 == 1) ? {t1[27:0], 4'h0} : t1;
|
||||
assign t3 = C1[4] ? {t2[15:0], 16'h0} : t2;
|
||||
assign Add = (~p & (op == 8));
|
||||
assign Sub = (~p & (op == 9));
|
||||
assign Mul = (~p & (op == 10));
|
||||
assign Div = (~p & (op == 11));
|
||||
assign Fadd = (~p & (op == 12));
|
||||
assign Fsub = (~p & (op == 13));
|
||||
assign Fmul = (~p & (op == 14));
|
||||
assign Fdiv = (~p & (op == 15));
|
||||
assign Ldr = ((p & ~q) & ~u);
|
||||
assign Str = ((p & ~q) & u);
|
||||
assign Br = (p & q);
|
||||
always @ (posedge clk) begin PC <= pcmux;
|
||||
IR <= stall ? IR : codebus;
|
||||
N <= regwr ? regmux[31] : N;
|
||||
Z <= regwr ? (regmux == 0) : Z;
|
||||
C <= Add ? (((sb & sc) | ((~sa & ~sb) & sc)) | (((~sa & sb) & ~sc) & sa)) : Sub ? (((~sb & sc) | ((sa & ~sb) & ~sc)) | ((sa & sb) & sc)) : C;
|
||||
OV <= Add ? (((sa & ~sb) & ~sc) | ((~sa & sb) & sc)) : Sub ? (((sa & ~sb) & sc) | ((~sa & sb) & ~sc)) : OV;
|
||||
stall1 <= stallX ? stall1 : stallL;
|
||||
PMsel <= (~rst | (pcmux[21:12] == 10'h3FF));
|
||||
R[ira0] <= regwr ? regmux : A;
|
||||
H <= Mul ? product[63:32] : Div ? remainder : H;
|
||||
end
|
||||
endmodule
|
||||
`timescale 1ns / 1 ps
|
||||
module RISC5( // translated from Lola
|
||||
input clk, rst, stallX,
|
||||
input [31:0] inbus, codebus,
|
||||
output [23:0] adr,
|
||||
output rd, wr, ben,
|
||||
output [31:0] outbus);
|
||||
reg [21:0] PC;
|
||||
reg [31:0] IR;
|
||||
reg N, Z, C, OV, stall1, PMsel;
|
||||
reg [31:0] R[15:0];
|
||||
reg [31:0] H;
|
||||
wire [21:0] pcmux, nxpc;
|
||||
wire cond, S, sa, sb, sc;
|
||||
wire [31:0] ins, pmout;
|
||||
wire p, q, u, v, w;
|
||||
wire [3:0] op, ira, ira0, irb, irc;
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wire [2:0] cc;
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wire [15:0] imm;
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wire [19:0] off;
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wire [23:0] offL;
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wire regwr, stall, stallL, stallM, stallD, stallFA, stallFM, stallFD;
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wire [1:0] sc1, sc0;
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wire a0, a1, a2, a3;
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wire [7:0] inbusL, outbusB0, outbusB1, outbusB2, outbusB3;
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wire [23:0] inbusH;
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wire [31:0] A, B, C0, C1, aluRes, regmux, s1, s2, s3, t1, t2, t3, quotient, remainder;
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wire [63:0] product;
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wire [31:0] fsum, fprod, fquot;
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wire Add, Sub, Mul, Div, Fadd, Fsub, Fmul, Fdiv, Ldr, Str, Br;
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||||
assign adr = stallL ? (B[23:0] + {4'h0, off}) : {pcmux, 2'h0};
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assign rd = ((Ldr & ~stallX) & ~stall1);
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assign wr = ((Str & ~stallX) & ~stall1);
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||||
assign ben = ((((p & ~q) & v) & ~stallX) & ~stall1);
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||||
assign outbus = {outbusB3, outbusB2, outbusB1, outbusB0};
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||||
PROM PM(.clk(clk), .adr(pcmux[8:0]), .data(pmout));
|
||||
Multiplier mulUnit(.clk(clk), .run(Mul), .u(~u), .stall(stallM), .x(B), .y(C1), .z(product));
|
||||
Divider divUnit(.clk(clk), .run(Div), .u(~u), .stall(stallD), .x(B), .y(C1), .quot(quotient), .rem(remainder));
|
||||
FPAdder faddUnit(.clk(clk), .run((Fadd | Fsub)), .u(u), .v(v), .stall(stallFA), .x(B), .y({(Fsub ^ C0[31]), C0[30:0]}), .z(fsum));
|
||||
FPMultiplier fmulUnit(.clk(clk), .run(Fmul), .stall(stallFM), .x(B), .y(C0), .z(fprod));
|
||||
FPDivider fdivUnit(.clk(clk), .run(Fdiv), .stall(stallFD), .x(B), .y(C0), .z(fquot));
|
||||
assign pcmux = ~rst ? 22'h3FF800 : stall ? PC : ((Br & cond) & u) ? (offL[21:0] + nxpc) : ((Br & cond) & ~u) ? C0[23:2] : nxpc;
|
||||
assign nxpc = (PC + 1);
|
||||
assign cond = (ins[27] ^ (((((((((cc == 0) & N) | ((cc == 1) & Z)) | ((cc == 2) & C)) | ((cc == 3) & OV)) | ((cc == 4) & (C | Z))) | ((cc == 5) & S)) | ((cc == 6) & (S | Z))) | (cc == 7)));
|
||||
assign S = (N ^ OV);
|
||||
assign sa = aluRes[31];
|
||||
assign sb = B[31];
|
||||
assign sc = C1[31];
|
||||
assign ins = PMsel ? pmout : IR;
|
||||
assign p = ins[31];
|
||||
assign q = ins[30];
|
||||
assign u = ins[29];
|
||||
assign v = ins[28];
|
||||
assign w = ins[16];
|
||||
assign op = ins[19:16];
|
||||
assign ira = ins[27:24];
|
||||
assign ira0 = Br ? 4'hF : ira;
|
||||
assign irb = ins[23:20];
|
||||
assign irc = ins[3:0];
|
||||
assign cc = ins[26:24];
|
||||
assign imm = ins[15:0];
|
||||
assign off = ins[19:0];
|
||||
assign offL = ins[23:0];
|
||||
assign regwr = (((~p & ~stall) | ((Ldr & ~stallX) & ~stall1)) | (((Br & cond) & v) & ~stallX));
|
||||
assign stall = ((((((stallL | stallM) | stallD) | stallFA) | stallFM) | stallFD) | stallX);
|
||||
assign stallL = ((Ldr | Str) & ~stall1);
|
||||
assign sc1 = C1[3:2];
|
||||
assign sc0 = C1[1:0];
|
||||
assign a0 = (~adr[1] & ~adr[0]);
|
||||
assign a1 = (~adr[1] & adr[0]);
|
||||
assign a2 = (adr[1] & ~adr[0]);
|
||||
assign a3 = (adr[1] & adr[0]);
|
||||
assign inbusL = (~ben | a0) ? inbus[7:0] : a1 ? inbus[15:8] : a2 ? inbus[23:16] : inbus[31:24];
|
||||
assign outbusB0 = A[7:0];
|
||||
assign outbusB1 = (ben & a1) ? A[7:0] : A[15:8];
|
||||
assign outbusB2 = (ben & a2) ? A[7:0] : A[23:16];
|
||||
assign outbusB3 = (ben & a3) ? A[7:0] : A[31:24];
|
||||
assign inbusH = ~ben ? inbus[31:8] : 24'h0;
|
||||
assign A = R[ira0];
|
||||
assign B = R[irb];
|
||||
assign C0 = R[irc];
|
||||
assign C1 = q ? {{16{v}}, imm} : C0;
|
||||
assign aluRes = ~op[3] ? ~op[2] ? ~op[1] ? ~op[0] ? q ? ~u ? {{16{v}}, imm} : {imm, 16'h0} : ~u ? C0 : ~v ? H : {N, Z, C, OV, 20'h0, 8'h58} : t3 : s3 : ~op[1] ? ~op[0] ? (B & C1) : (B & ~C1) : ~op[0] ? (B | C1) : (B ^ C1) : ~op[2] ? ~op[1] ? ~op[0] ? ((B + C) + (u & C)) : ((B - C1) - (u & C)) : ~op[0] ? product[31:0] : quotient : ~op[1] ? fsum : ~op[0] ? fprod : fquot;
|
||||
assign regmux = Ldr ? {inbusH, inbusL} : (Br & v) ? {8'h0, nxpc, 2'h0} : aluRes;
|
||||
assign s1 = (sc0 == 3) ? {w ? B[2:0] : {3{B[31]}}, B[31:3]} : (sc0 == 2) ? {w ? B[1:0] : {2{B[31]}}, B[31:2]} : (sc0 == 1) ? {w ? B[0] : B[31], B[31:1]} : B;
|
||||
assign s2 = (sc1 == 3) ? {w ? s1[11:0] : {12{B[31]}}, s1[31:12]} : (sc1 == 2) ? {w ? s1[7:0] : {8{B[31]}}, s1[31:8]} : (sc1 == 1) ? {w ? s1[3:0] : {4{B[31]}}, s1[31:4]} : s1;
|
||||
assign s3 = C1[4] ? {w ? s2[15:0] : {16{s2[31]}}, s2[31:16]} : s2;
|
||||
assign t1 = (sc0 == 3) ? {B[28:0], 3'h0} : (sc0 == 2) ? {B[29:0], 2'h0} : (sc0 == 1) ? {B[30:0], 1'h0} : B;
|
||||
assign t2 = (sc1 == 3) ? {t1[19:0], 12'h0} : (sc1 == 2) ? {t1[23:0], 8'h0} : (sc1 == 1) ? {t1[27:0], 4'h0} : t1;
|
||||
assign t3 = C1[4] ? {t2[15:0], 16'h0} : t2;
|
||||
assign Add = (~p & (op == 8));
|
||||
assign Sub = (~p & (op == 9));
|
||||
assign Mul = (~p & (op == 10));
|
||||
assign Div = (~p & (op == 11));
|
||||
assign Fadd = (~p & (op == 12));
|
||||
assign Fsub = (~p & (op == 13));
|
||||
assign Fmul = (~p & (op == 14));
|
||||
assign Fdiv = (~p & (op == 15));
|
||||
assign Ldr = ((p & ~q) & ~u);
|
||||
assign Str = ((p & ~q) & u);
|
||||
assign Br = (p & q);
|
||||
always @ (posedge clk) begin PC <= pcmux;
|
||||
IR <= stall ? IR : codebus;
|
||||
N <= regwr ? regmux[31] : N;
|
||||
Z <= regwr ? (regmux == 0) : Z;
|
||||
C <= Add ? (((sb & sc) | ((~sa & ~sb) & sc)) | (((~sa & sb) & ~sc) & sa)) : Sub ? (((~sb & sc) | ((sa & ~sb) & ~sc)) | ((sa & sb) & sc)) : C;
|
||||
OV <= Add ? (((sa & ~sb) & ~sc) | ((~sa & sb) & sc)) : Sub ? (((sa & ~sb) & sc) | ((~sa & sb) & ~sc)) : OV;
|
||||
stall1 <= stallX ? stall1 : stallL;
|
||||
PMsel <= (~rst | (pcmux[21:12] == 10'h3FF));
|
||||
R[ira0] <= regwr ? regmux : A;
|
||||
H <= Mul ? product[63:32] : Div ? remainder : H;
|
||||
end
|
||||
endmodule
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue