Update confidence tests for arg handling move. Remove unused vars in Platform.

This commit is contained in:
David Brown 2016-12-01 18:39:02 +00:00
parent 299b0636ad
commit c65b89daf3
4 changed files with 4 additions and 10 deletions

View file

@ -22,9 +22,6 @@ VAR
LittleEndian-: BOOLEAN;
PID-: INTEGER; (* Note: Must be updated by Fork implementation *)
CWD-: ARRAY 256 OF CHAR;
ArgCount-: INTEGER;
ArgVector-: SYSTEM.ADDRESS;
TimeStart: LONGINT;
SeekSet-: INTEGER;
@ -426,7 +423,6 @@ PROCEDURE -getpid(): INTEGER "(INTEGER)getpid()";
BEGIN
TestLittleEndian;
HaltHandler := NIL;
TimeStart := 0; TimeStart := Time();
PID := getpid();
IF getcwd(CWD) = NIL THEN CWD := "" END;

View file

@ -35,8 +35,6 @@ VAR
StdOut-: FileHandle;
StdErr-: FileHandle;
InterruptHandler: SignalHandler;
NL-: ARRAY 3 OF CHAR; (* Platform specific newline representation *)

View file

@ -1,7 +1,7 @@
MODULE Lola; (* Command line runner for Lola to verilog compilation *)
IMPORT LSB, LSC, LSV, Platform, Console;
IMPORT LSB, LSC, LSV, Modules, Console;
BEGIN
IF Platform.ArgCount < 3 THEN
IF Modules.ArgCount < 3 THEN
Console.String("Lola - compile lola source to verilog source."); Console.Ln; Console.Ln;
Console.String("usage:"); Console.Ln; Console.Ln;
Console.String(" lola lola-source-file verilog-source-file"); Console.Ln; Console.Ln;

View file

@ -1,6 +1,6 @@
(* Test that interrupt and quit are handled correctly. *)
MODULE SignalTest;
IMPORT Console, Platform, Files, SYSTEM;
IMPORT Console, Platform, Modules, Files, SYSTEM;
VAR result: Files.File; rider: Files.Rider;
@ -42,7 +42,7 @@ END Take5;
BEGIN
result := Files.New("result");
Files.Set(rider, result, 0);
IF Platform.ArgCount > 1 THEN
IF Modules.ArgCount > 1 THEN
Platform.SetInterruptHandler(handle);
Platform.SetQuitHandler(handle)
END;